System and methods using a multiplexed reference for sense amplifiers

• US 9,202,543 B2
• Filed: 11/30/2012
• Issued: 12/01/2015
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG, Intel Deutschland GmbH (Intel Corporation)
• Inventors: Boujamaa, El Mehdi, Dray, Cyrille
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US13/689,869
• Publication Number:
  US 20140153313A1
• Time in Patent Office: 1,096 Days
• Field of Search: 365/148, 365/158, 365/163, 365/171, 365/173, 365/185.2, 365/185.21, 365/202, 365/206, 365/207, 365/210.1, 365/210.11, 365/210.14
• US Class Current: 1/1
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A sense amplifier system includes a first path, a second path, a memory cell, a first reference cell, a second reference cell, and a switch component. The switch component is configured to switch connections between the first and second reference cells and the first and second paths according to a sampling phase and an amplification phase.

Claims

1. A sense amplifier system comprising:

a switch component coupled to a sense path,

a reference path, wherein the sense path and the reference path are different paths;

a memory cell;

a first reference cell;

a second reference cell, wherein the second reference cell has a different resistivity than the first reference cell; and

wherein the switch component is configured to switch connections between the first and second reference cells, the memory cell, the sense path and the reference path according to a sampling phase and an amplification phase, wherein the sense path is connected to the first reference cell during the sampling phase and the reference path is connected to the second reference cell during the amplification phase.

2. The system of claim 1, wherein the switch component is configured to connect the reference path to the memory cell during the sampling phase.

3. The system of claim 2, wherein the switch component is configured to connect the sense path to the memory cell during the amplification phase.

4. The system of claim 2, wherein the switch component is a multiplexor.

5. The system of claim 1, wherein the sense path and the reference path include a cascode component.

6. The system of claim 5, further comprising bias capacitors coupled to the cascode component, wherein the bias capacitors are configured to set gate voltages of cascode transistors of the cascode component.

7. The system of claim 1, wherein the sense path includes an offset capacitor configured to sense an offset during the sampling phase.

8. The system of claim 1, further comprising a common mode feedback structure coupled to the sense path and the reference path, the common mode feedback structure configured to provide a common mode feedback mode of operation.

9. The system of claim 8, further comprising a latch structure coupled to the common mode feedback structure, the first path, and the second path, the latch structure configured to provide a latch mode of operation.

10. The system of claim 1, wherein the first reference cell is a high resistivity reference cell.

11. The system of claim 1, wherein the first reference cell is a low resistivity reference cell and the second reference cell is a high resistivity reference cell, wherein the first reference cell is configured to enable a low resistivity reference current and the second reference cell is configured to enable a high resistivity reference current.

12. The system of claim 1, wherein the sense path includes a first differential output node and the reference path includes a second differential output node, wherein the first and second differential output nodes provide an output voltage during the amplification phase representative of a logical content of the memory cell.

13. A sense amplifier system comprising:

a sense path including a first transistor coupled to a first data transistor;

a reference path including a second transistor coupled to a second data transistor;

a first reference cell and a second reference cell, wherein the first reference cell and the second reference cell are configured to generate reference currents having different values; and

a switch component coupled to the sense path and the reference path, the switch component configured to connect a memory cell to the reference path and the first reference cell to the sense path during a first phase and to connect the memory cell to the sense path and the second reference cell to the reference path during a second phase.

14. The system of claim 13, wherein the first phase is a sampling phase.

15. The system of claim 13, wherein the sense path is configured to have a first reference current and the reference path is configured to have a data current during the first phase.

16. The system of claim 15, wherein the sense path is configured to have the data current and the reference path is configured to have a second reference current during the second phase, wherein the second reference current is varied from the first reference current.

17. The system of claim 16, wherein the first reference current is a high resistivity reference current and the second reference current is a low resistivity reference current.

18. A method of operating a sense amplifier, the method comprising:

generating a first reference current in a sampling phase;

generating a second reference current in an amplification phase, wherein a value of the second reference current is different than a value of the first reference current;

generating a data current;

connecting a sense path to the first reference current in the sampling phase;

connecting a reference path to the second reference current in the amplification phase; and

generating an output voltage according to the data current, the first reference current, and the second reference current.

19. The method of claim 18, further comprising providing a memory cell, wherein the memory cell is utilized to generate the data current and the output voltage represents a content of the memory cell.

20. The method of claim 18, wherein generating the first reference current comprises using a low resistivity reference cell.

21. The method of claim 18, wherein generating the first reference current comprises connecting the sense path to a first reference cell.

22. The method of claim 20, wherein generating the second reference current comprises connecting the reference path to a second reference cell.