Efficient PCMS refresh mechanism

• US 9,202,548 B2
• Filed: 12/22/2011
• Issued: 12/01/2015
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Faber, Robert W.
• Primary Examiner(s): Lam, David
• Application Number:
  US13/997,661
• Publication Number:
  US 20140204663A1
• Time in Patent Office: 1,440 Days
• Field of Search: 365/163, 365/222, 36518914-18916, 711/105
• US Class Current: 1/1
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement

Abstract

An apparatus is described having invert determination logic circuitry to determine if a read data path that transports data read from a PCMS memory device is to be inverted or not inverted as a function of whether information represented by the data was last written in an inverted or non inverted logical state to the PCMS memory device during a refresh of said PCMS memory device.

Claims

1. An apparatus, comprising:

invert determination logic circuitry to determine if a read data path that transports data read from a memory device is to be inverted or not inverted as a function of whether information represented by said data was last written in an inverted or non inverted logical state to said memory device during a refresh of said memory device, said memory device comprising vertically stacked storage cell arrays.

2. The apparatus of claim 1 wherein said read data path comprises a first selectable path having a bank of inverters to invert data read from said memory device, and, a second selectable path that does not invert data read from said memory device, said invert determination logic circuitry to provide a signal that establishes which one of said selectable paths is selected.

3. The apparatus of claim 2 further comprising refresh control logic circuitry having circuitry to determine when a next refresh cycle of a group of addresses of said memory device are to be refreshed.

4. The apparatus of claim 1 wherein said invert determination logic circuitry has first logic circuitry to determine if said read data path is to be inverted for a refresh, and, has second logic circuitry to determine if said read data path is to be inverted for a read or write transaction.

5. The apparatus of claim 1 further comprising a register that is indicative of whether said data was last written in an inverted or non inverted state to said memory device during said refresh of said memory device.

6. The apparatus of claim 1 further comprising refresh control logic circuitry to enable, during said refresh of said memory device, a loopback from said read data path to a write data path that transports write data to be written to said device.

7. The apparatus of claim 6 wherein said write data path comprises a first selectable path having a bank of inverters to invert data to be written to said memory device, and, a second selectable path that does not invert data to be written to said memory device, said invert determination circuitry to ensure that one but not both of said data paths inverts its respective data during said refresh of said memory device.

8. A method, comprising:

reading data from a memory device, the memory device comprising vertically stacked storage cell arrays;

inverting said data to form inverted data;

writing said inverted data into said memory device at a same address that said data was read from; and

,

recording invert/non-invert information that indicates whether said inverted data represents an inverted form or non inverted form of information stored at said same address.

9. The method of claim 8 further comprising determining that a next refresh is appropriate.

10. The method of claim 9, further comprising, as a consequence of said determining:

reading said inverted data from said memory device from said same address;

inverting said inverted data to form twice inverted data;

writing said twice inverted twice data into said memory device at said address; and

,

toggling said invert/non-invert information and recording the result.

11. The method of claim 9 further comprising:

a) reading said inverted data and referring to said invert/non-invert information;

b) inverting said inverted data if said invert/non-invert information indicates said inverted data represents an inverted form of said information, or, not inverting said inverted data if said invert/non-invert information indicates said inverted data represents a non inverted form of said information;

c) writing a resultant of b) into said memory device at said same address if b) included inverting said inverted data, or, writing an inverted form of a resultant of b) into said memory device at said same address if b) included not inverting said inverted data.

12. The method of claim 11 further comprising, after b) but before c), performing error detection and recovery followed by a CRC calculation on information produced by b) to form said resultant of b).

13. The method of claim 8 further comprising:

receiving a read transaction for said same address;

comparing said same address to an address of a refresh cycle;

referring to said invert/non-invert information; and

,

performing a second read of said memory device at said same address to satisfy said read transaction and performing one of the following;

i) inverting data received from said second read if said invert/non-invert information indicated said inverted data represents an inverted form of said information and said same address is behind said refresh cycle;

ii) inverting data received from said second read if said invert/non-invert information indicated said inverted data represents a non inverted form of said information and said same address is ahead of said refresh cycle;

iii) not inverting data received from said second read if said invert/non-invert information indicated said inverted data represents a non inverted form of said information and said address is behind said refresh cycle;

iv) not inverting data received from said second read if said invert/non-invert information indicated said inverted data represents an inverted form of said information and said address is ahead of said refresh cycle.

14. The method of claim 13 further comprising updating said invert/non-invert information when said refresh cycle is complete.

15. The method of claim 8 further comprising:

receiving a write transaction with write data for said same address;

comparing said same address to a current address of said refresh cycle;

referring to said invert/non-invert information; and

,

satisfying said write transaction by performing one of the following;

i) inverting said write data if said invert/non-invert information indicated said inverted data represents an inverted form of said information and said same address is behind of said refresh cycle;

ii) inverting said write data if said invert/non-invert information indicated said inverted data represents a non inverted form of said information and said same address is ahead of said refresh cycle;

iii) not inverting said write data if said invert/non-invert information indicated said inverted data represents a non inverted form of said information and said address is behind said refresh cycle;

iv) not inverting said write data if said invert/non-invert information indicated said inverted data represents an inverted form of said information and said address is ahead of said refresh cycle.

16. The method of claim 15 further comprising updating said invert/non-invert information when said refresh cycle is complete.

17. A computing system, comprising:

a near memory composed of a DRAM device;

a far memory composed of a memory device, the memory device comprising vertically stacked storage cell arrays;

an NVRAM controller coupled to said memory device, said NVRAM controller comprising invert determination logic circuitry to determine if a read data path that transports data read from said memory device is to be inverted or not inverted as a function of whether information represented by the data was last written in an inverted or non inverted logical state to said memory device during a refresh of said memory device.

18. The computing system of claim 17 wherein said read data path comprises a first selectable path having a bank of inverters to invert data read from said memory device, and, a second selectable path that does not invert data read from said memory device, said invert determination circuitry to provide a signal that establishes which one of said selectable paths is selected.

19. The computing system of claim 18 further comprising refresh control logic circuitry having circuitry to determine when a next refresh cycle of a group of addresses of said memory device are to be refreshed.

20. The computing system of claim 17 wherein said invert determination logic circuitry has first logic circuitry to determine if said read data path is to be inverted for a refresh, and, has second logic circuitry to determine if said read data path is to be inverted for a read or write transaction.

21. The computing system of claim 18 further comprising a register that is indicative of whether said data was last written in an inverted or non inverted state to said memory device during said refresh of said memory device.

22. The computing system of claim 17 further comprising refresh control logic circuitry to enable, during said refresh of said memory device, a loopback from said read data path to a write data path that transports write data to be written to said memory device.