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Efficient PCMS refresh mechanism

  • US 9,202,548 B2
  • Filed: 12/22/2011
  • Issued: 12/01/2015
  • Est. Priority Date: 12/22/2011
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • invert determination logic circuitry to determine if a read data path that transports data read from a memory device is to be inverted or not inverted as a function of whether information represented by said data was last written in an inverted or non inverted logical state to said memory device during a refresh of said memory device, said memory device comprising vertically stacked storage cell arrays.

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