Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays

• US 9,202,574 B2
• Filed: 09/26/2013
• Issued: 12/01/2015
• Est. Priority Date: 03/08/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Liu, Zengtao
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US14/037,488
• Publication Number:
  US 20140036586A1
• Time in Patent Office: 796 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

In an embodiment, a memory device may have a plurality of layers of memory cell arrays. Each layer may have a plurality of strings of memory cells and a different source line coupled to each layer of the plurality of layers.

Claims

1. A memory device comprising:

a plurality of layers of memory cell arrays, each layer of the plurality of layers comprising;

a plurality of strings of memory cells;

wherein each layer of the plurality of layers is coupled to a single source line and a single data line; and

wherein the memory device is configured to bias each single source line with a respective source line voltage responsive to a programming rate for that respective layer.

2. The memory device of claim 1 and further including an access line coupled to a particular row of memory cells wherein the access line is common to the particular row of each of the plurality of layers.

3. The memory device of claim 1 wherein the memory device is configured to select a particular layer of the plurality of layers responsive to biasing the single data line coupled to the particular layer.

4. The memory device of claim 1 and further including a select gate source line that is common to all of the layers of the plurality of layers.

5. The memory device of claim 1 and further including a select gate drain line that is common to a particular one of a plurality of select gate drain transistors for each of the plurality of layers of memory cell arrays.

7. The memory device of claim 1, wherein the memory device is coupled to a controller.

6. A memory device comprising:

a plurality of layers of memory cell arrays, each layer of the plurality of layers comprising;

a plurality of strings of memory cells;

wherein each layer of the plurality of layers is coupled to a single source line and a single data line; and

wherein the memory device is configured to shift a target threshold voltage range of a layer responsive to a programming rate for that layer.

8. A memory device comprising:

a plurality of layers of memory cell arrays, each layer of the plurality of layers comprising;

a plurality of strings of memory cells;

a single data line coupled to each layer of the plurality of layers;

wherein the plurality of layers are arranged in a plurality of groups of the layers, where each group of the layers is coupled to a single source line; and

wherein each group of the layers comprises at least two of the layers of the plurality of layers;

wherein the memory device is configured to bias each single source line with a source line voltage that is responsive to a programming rate for its respective group of the layers.

9. A memory device comprising:

a plurality of layers of memory cell arrays, each layer comprising;

a plurality of strings of memory cells;

a different source line coupled to a different group of layers of the plurality of layers, wherein each group of layers comprises at least one of the layers; and

a plurality of data lines, a respective data line coupled to each layer of the plurality of layers wherein the memory device is configured to select a respective layer responsive to biasing of a respective one of the data lines and further wherein the data lines are grouped according to the plurality of layers coupled to a particular source line and the data lines within a particular group at substantially the same voltage;

wherein the memory device is configured to bias data lines coupled to a particular group of layers having a relatively slower programming rate at a higher voltage than data lines coupled to a group of layers having a relatively faster programming rate.

12. The memory device of claim 9 wherein respective groups of the layers of the plurality of groups of the layers have different numbers of the layers.

10. A memory device comprising:

a plurality of layers of memory cell arrays, each layer comprising;

a plurality of strings of memory cells;

a different source line coupled to each layer of the plurality of layers; and

a different data line coupled to each layer of the plurality of layers so that the plurality of strings in each layer is between the data line and the source line coupled to that layer;

wherein the memory device is configured to bias each different source line with a respective source line voltage responsive to a programming rate for that respective layer.

11. A memory device comprising:

a plurality of layers of memory cell arrays, each layer comprising;

a plurality of strings of memory cells;

a different source line coupled to each layer of the plurality of layers; and

a different data line coupled to each layer of the plurality of layers so that the plurality of strings in each layer is between the data line and the source line coupled to that layer;

wherein the memory device is configured to bias each different source line with a respective source line voltage and each different data line with a respective data line voltage so that a difference between the respective source line voltage and the respective data line voltage is the same for each layer.