Method for providing a gate metal layer of a transistor device and associated transistor

• US 9,202,695 B2
• Filed: 05/07/2014
• Issued: 12/01/2015
• Est. Priority Date: 05/07/2013
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Togo, Mitsuhiro
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): SYLVIA, CHRISTINA A
• Application Number:
  US14/271,956
• Publication Number:
  US 20140332864A1
• Time in Patent Office: 573 Days
• Field of Search: 438/592, 438/595, 257/392, 257/E21.631, 257/E21.632
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method includes providing a dummy gate structure on a substrate. The dummy gate structure includes a gate dielectric layer and a dummy gate electrode layer, and is laterally defined by inner sidewalls of a set of spacers. The method also includes laterally embedding the dummy gate structure, removing the dummy gate electrode, and providing a final gate electrode layer in between the inner sidewalls of the set of spacers. Providing the final gate electrode layer further includes providing a diffusion layer that extends on top of the gate dielectric layer, on inner sidewalls of the spacers, and on a portion of a front surface of embedding layers for the dummy gate structure. Providing the final gate electrode also includes providing a metal on top of the diffusion layer, applying an anneal step, and filling the area in between the inner sidewalls of the set of spacers with a final gate metal filling layer. The present disclosure also relates to an associated transistor.

Claims

1. A method for manufacturing a field effect transistor, the method comprising the steps of:

providing a dummy gate structure on a substrate, the dummy gate structure comprising a gate dielectric layer, the dummy gate structure being laterally defined by a gate trench defined by inner sidewalls of a set of spacers;

laterally embedding the dummy gate structure by one or more embedding layers, the one or more embedding layers defining a front surface;

and

providing a final gate electrode layer in between the inner sidewalls of the set of spacers;

and wherein providing the final gate electrode layer further comprises;

providing a diffusion layer, the diffusion layer extending at least on top of the gate dielectric layer, on inner sidewalls of the set of spacers, and on at least a portion of the front surface;

providing a metal layer including a metal on top of a portion of the diffusion layer that is disposed over the front surface, and whereby the metal does not enter the gate trench;

applying an anneal step, the anneal step being adapted for driving diffusion of the metal of the metal layer into the diffusion layer, and for further diffusing the metal in the diffusion layer towards the portion of the diffusion layer in the area corresponding to the area of the gate dielectric; and

filling the area in between the inner sidewalls of the set of spacers with a final gate metal filling layer.

2. The method according to claim 1, wherein the diffusion layer comprises silicon.

3. The method according to claim 1, wherein the diffusion layer has a thickness within the range of 2 to 10 nm.

4. The method according to claim 1, wherein the metal layer comprises Aluminium, Indium, Gallium, or Nickel.

5. The method according to claim 1, wherein the anneal step is performed at a temperature between 400°

C. and 600°

C.

6. The method according to claim 1, wherein the anneal step has a duration of 1 to 10 minutes.

7. The method according to claim 1, wherein a horizontal distance between the inner sidewalls of the spacers is smaller than 20 nm.

8. The method according to claim 1, wherein the diffusion layer is deposited by means of Chemical Vapor Deposition (CVD).

9. The method according to claim 1, wherein the anneal step is such that the diffusion layer and the metal layer merge completely into a single merged layer of mixed constitution.

10. The method according to claim 1, further comprising performing a Chemical Mechanical Polishing (CMP) step after applying the anneal step and filling the area in between the inner sidewalls of the set of spacers with a final gate metal filling layer.

11. The method according to claim 1, wherein a vertical distance between the metal layer on the front surface, and an upper surface of the diffusion layer in an area on top of the gate dielectric layer is smaller than 170 nm.

12. The method according to claim 1, wherein the dummy gate structure further includes a dummy gate electrode layer, wherein the method further comprises removing the dummy gate electrode layer in between the inner sidewalls of the set of spacers, and wherein the final gate electrode layer replaces the dummy gate electrode layer.

13. The method according to claim 1, wherein the field effect transistor is a non-planar type that includes at least one FIN structure protruding from a front surface of the substrate, and wherein the dummy gate structure is provided at least partially on the FIN structure and at least partially adjacent to the FIN structure.