Defect pattern evaluation method, defect pattern evaluation apparatus, and recording media

• US 9,202,763 B2
• Filed: 03/14/2013
• Issued: 12/01/2015
• Est. Priority Date: 01/16/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Miyoshi, Seiro, Aritake, Toshiyuki
• Primary Examiner(s): Chu, Randolph I
• Application Number:
  US13/829,200
• Publication Number:
  US 20140199792A1
• Time in Patent Office: 992 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01J 2237/24592 Inspection and quality control of devices
• CPC Class Codes: H01J 2237/2817 Pattern inspection
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

According to a defect pattern evaluation method of an embodiment, defects are detected by performing optical defect inspection on a pattern on a substrate. Then, the defects are classified according to a type of a pattern layout using a pattern layout corresponding to coordinates of the defects. Further, a computer calculates a defect occurrence rate by dividing the number of defects of each pattern layout by an arrangement number of the pattern layouts in an inspection region. Then, the defect occurrence rate of each pattern layout is output as an evaluation result.

Claims

1. A defect pattern evaluation method, comprising:

performing, after a predetermined process for manufacturing a semiconductor device, optical defect inspection on a pattern on a substrate;

detecting defects by the optical defect inspection;

classifying, on the basis of a pattern layout that corresponds to coordinates of the defects, the defects by a type of the pattern layout;

counting a number of the defects that are in each type of the pattern layout;

calculating, using a computer, a defect occurrence rate for each type of the pattern layout by dividing the number of defects counted in each type of the pattern layout by a number of pattern layouts in each type of the pattern layout; and

outputting the defect occurrence rate for each of the pattern layout as an evaluation result.

2. The defect pattern evaluation method according to claim 1, further comprising:

extracting a predetermined number of defects from the defects based on a classification result of the pattern layout;

observing the extracted defects through a scanning electron microscope (SEM);

extracting a systematic defect occurring depending on the type of the pattern layout from the defects based on an observation result; and

outputting the number of the pattern layouts in which the systematic defect has occurred and the number of types of the pattern layouts in which the systematic defect has occurred.

3. The defect pattern evaluation method according to claim 1, further comprising:

ranking the pattern layouts based on the height of the defect occurrence rate; and

outputting the ranking of each pattern layout.

4. The defect pattern evaluation method according to claim 1, further comprising:

preferentially extracting a defect of a pattern layout which is high in the defect occurrence rate from the defects, and observing the extracted defect through the SEM.

5. The defect pattern evaluation method according to claim 1, further comprising:

forming the pattern on the substrate in a process condition set to each shot;

determining whether or not there is a pattern layout in which the systematic defect has occurred for each shot;

determining whether or not the process condition is acceptable for each shot based on a determination result;

obtaining a process margin based on an acceptance determination result; and

outputting the process margin.

6. The defect pattern evaluation method according to claim 5, further comprising:

determining the process margin for each pattern layout; and

synthesizing the acceptance determination result to obtain the process margin.

7. The defect pattern evaluation method according to claim 2, further comprising:

excluding a false defect and a random defect from the defects and extracting the systematic defect.

8. The defect pattern evaluation method according to claim 1,

wherein the optical defect inspection is performed after a lithography, a hard mask process, gate pattern forming, or interconnection pattern forming.

9. A defect pattern evaluation apparatus, comprising:

a classifying unit that classifies, on the basis of a pattern layout that corresponds to coordinates of defects, the defects by a type of the pattern layout, the defects being detected by performing, after a predetermined process for manufacturing a semiconductor device, optical defect inspection on a pattern on a substrate;

a counting unit that counts a number of defects that are in each type of the pattern layout;

a defect occurrence rate calculating unit that calculates a defect occurrence rate for each type of the pattern layout by dividing the number of defects counted in each type of the pattern layout by a number of pattern layouts in each type of the pattern layout; and

an output unit that outputs the defect occurrence rate for each type of the pattern layout as an evaluation result.

10. The defect pattern evaluation apparatus according to claim 9, further comprising:

an evaluating unit that extracts a systematic defect occurring depending on the type of the pattern layout from the defects using an SEM observation result of defects extracted based on a classification result of the pattern layout,

wherein the evaluating unit calculates the number of pattern layouts in which the systematic defect has occurred and the number of types of the pattern layouts in which the systematic defect has occurred, and outputs a calculation result to the output unit.

11. The defect pattern evaluation apparatus according to claim 9,

wherein the evaluating unit ranks the pattern layout based on the height of the defect occurrence rate, and outputs ranking of each pattern layout to the output unit.

12. The defect pattern evaluation apparatus according to claim 9,

wherein when the pattern is formed on the substrate in a process condition set to each shot,

the evaluating unit determines whether or not there is a pattern layout in which the systematic defect has occurred for each shot, determines whether or not the process condition is acceptable for each shot based on a determination result, obtains a process margin based on an acceptance determination result, and outputs the process margin to the output unit.

13. The defect pattern evaluation apparatus according to claim 12,

wherein the evaluating unit determines the process margin for each pattern layout and obtains the process margin by synthesizing the acceptance determination result.

14. The defect pattern evaluation apparatus according to claim 10,

wherein the evaluating unit excludes a false defect or random defect from the defects, and extracts the systematic defect.

15. A non-transitory computer-readable recording medium on which a defect evaluation program is recorded, the defect evaluation program causing a computer to evaluate a pattern on a substrate which has been subjected to, after a predetermined process for manufacturing a semiconductor device, optical defect inspection, the defect evaluation program causing the computer to execute:

classifying, on the basis of a pattern layout that corresponds to coordinates of defects detected by the optical defect inspection, the defects by a type of the pattern layout;

counting a number of defects that are in each type of the pattern layout;

calculating a defect occurrence rate for each type of the pattern layout by dividing the number of defects counted in each type of the pattern layout by a number of pattern layouts in each type of the pattern layout; and

outputting the defect occurrence rate for each type of the pattern layout as an evaluation result.

16. The recording media according to claim 15,

wherein the defect evaluation program causes the computer to further execute:

extracting a systematic defect occurring depending on the type of the pattern layout from the defects using an SEM observation result of defects extracted based on a classification result of the pattern layout; and

outputting the number of pattern layouts in which the systematic defect has occurred and the number of types of the pattern layouts in which the systematic defect has occurred.

17. The recording media according to claim 15,

wherein the defect evaluation program causes the computer to further execute:

ranking the pattern layout based on the height of the defect occurrence rate; and

outputting ranking of each pattern layout.

18. The recording media according to claim 15,

wherein the defect evaluation program causes the computer to further execute:

when the pattern is formed on the substrate in a process condition set to each shot,

determining whether or not there is a pattern layout in which the systematic defect has occurred for each shot;

determining whether or not the process condition is acceptable for each shot based on a determination result;

obtaining a process margin based on an acceptance determination result; and

outputting the process margin.

19. The recording media according to claim 18,

wherein the defect evaluation program causes the computer to further execute:

determining the process margin for each pattern layout; and

obtaining the process margin by synthesizing the acceptance determining result.

20. The recording media according to claim 16,

wherein the defect evaluation program causes the computer to further execute:

extracting the systematic defect by excluding a false defect or a random defect from the defects when the systematic defect is extracted.