Well resistors and polysilicon resistors
First Claim
1. A method of forming an integrated circuit, comprising the steps:
- providing a substrate comprising semiconductor material at a top surface of the substrate;
forming a chemical mechanical polish (CMP) stop layer over the substrate;
forming an STI mask over the CMP stop layer, the STI mask covering areas for active areas of the integrated circuit, the active areas including resistor head active areas in an area for a well resistor and including resistor dummy active areas in the area for the well resistor, the resistor dummy active areas having a density of 10 percent to 80 percent;
removing the CMP stop layer and removing a portion of the semiconductor material of the substrate in areas exposed by the STI mask to form STI trenches 250 nanometers to 500 nanometers deep in the substrate;
forming a layer of trench fill dielectric material in the STI trenches and over the CMP stop layer over the active areas, the trench fill dielectric material filling the STI trenches;
planarizing the trench fill dielectric material down to the CMP stop layer by a CMP process, wherein the CMP process removes all of the trench fill dielectric material from over the CMP stop layer and does not remove any of the semiconductor material from the resistor head active areas and the resistor dummy active areas;
removing a remaining portion of the CMP stop layer wherein the trench fill dielectric material in the STI trenches forms field oxide of the integrated circuit;
implanting well dopants through the field oxide into the semiconductor material of the substrate under the field oxide in the area for the well resistor;
heating the substrate in a well anneal process to activate the well dopants to form the well resistor; and
forming contacts to provide electrical connections to the well resistor through the resistor head active areas, wherein the resistor dummy active areas are free of electrical connections above the substrate.
1 Assignment
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Accused Products
Abstract
An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.
15 Citations
10 Claims
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1. A method of forming an integrated circuit, comprising the steps:
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providing a substrate comprising semiconductor material at a top surface of the substrate; forming a chemical mechanical polish (CMP) stop layer over the substrate; forming an STI mask over the CMP stop layer, the STI mask covering areas for active areas of the integrated circuit, the active areas including resistor head active areas in an area for a well resistor and including resistor dummy active areas in the area for the well resistor, the resistor dummy active areas having a density of 10 percent to 80 percent; removing the CMP stop layer and removing a portion of the semiconductor material of the substrate in areas exposed by the STI mask to form STI trenches 250 nanometers to 500 nanometers deep in the substrate; forming a layer of trench fill dielectric material in the STI trenches and over the CMP stop layer over the active areas, the trench fill dielectric material filling the STI trenches; planarizing the trench fill dielectric material down to the CMP stop layer by a CMP process, wherein the CMP process removes all of the trench fill dielectric material from over the CMP stop layer and does not remove any of the semiconductor material from the resistor head active areas and the resistor dummy active areas; removing a remaining portion of the CMP stop layer wherein the trench fill dielectric material in the STI trenches forms field oxide of the integrated circuit; implanting well dopants through the field oxide into the semiconductor material of the substrate under the field oxide in the area for the well resistor; heating the substrate in a well anneal process to activate the well dopants to form the well resistor; and forming contacts to provide electrical connections to the well resistor through the resistor head active areas, wherein the resistor dummy active areas are free of electrical connections above the substrate. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of forming an integrated circuit, comprising the steps:
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providing a substrate comprising semiconductor material at a top surface of the substrate; forming a CMP stop layer over the substrate; forming an STI mask over the CMP stop layer, the STI mask covering areas for active areas of the integrated circuit, the active areas including resistor dummy active areas in the area for a polysilicon resistor, the resistor dummy active areas having a density of 10 percent to 80 percent; removing the CMP stop layer and removing a portion of the semiconductor material of the substrate in areas exposed by the STI mask to form STI trenches 250 nanometers to 500 nanometers deep in the substrate; forming a layer of trench fill dielectric material in the STI trenches and over the CMP stop layer over the active areas, the trench fill dielectric material filling the STI trenches; planarizing the trench fill dielectric material down to the CMP stop layer by a CMP process, wherein the CMP process removes all of the trench fill dielectric material from over the CMP stop layer and does not remove any of the semiconductor material from the resistor dummy active areas; removing a remaining portion of the CMP stop layer wherein the trench fill dielectric material in the STI trenches forms field oxide of the integrated circuit; forming a layer of polysilicon over the field oxide and the resistor dummy active areas; planarizing the layer of polysilicon using a CMP process to form a CMP-planarized polysilicon layer; forming a polysilicon etch mask over the CMP-planarized polysilicon layer which defines the polysilicon resistor; removing polysilicon from the CMP-planarized polysilicon layer in areas outside the polysilicon etch mask to form the polysilicon resistor; and forming contacts to provide electrical connections to the polysilicon resistor, wherein the resistor dummy active areas are free of electrical connections above the substrate. - View Dependent Claims (8, 9, 10)
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Specification