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Well resistors and polysilicon resistors

  • US 9,202,859 B1
  • Filed: 05/27/2014
  • Issued: 12/01/2015
  • Est. Priority Date: 05/27/2014
  • Status: Active Grant
First Claim
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1. A method of forming an integrated circuit, comprising the steps:

  • providing a substrate comprising semiconductor material at a top surface of the substrate;

    forming a chemical mechanical polish (CMP) stop layer over the substrate;

    forming an STI mask over the CMP stop layer, the STI mask covering areas for active areas of the integrated circuit, the active areas including resistor head active areas in an area for a well resistor and including resistor dummy active areas in the area for the well resistor, the resistor dummy active areas having a density of 10 percent to 80 percent;

    removing the CMP stop layer and removing a portion of the semiconductor material of the substrate in areas exposed by the STI mask to form STI trenches 250 nanometers to 500 nanometers deep in the substrate;

    forming a layer of trench fill dielectric material in the STI trenches and over the CMP stop layer over the active areas, the trench fill dielectric material filling the STI trenches;

    planarizing the trench fill dielectric material down to the CMP stop layer by a CMP process, wherein the CMP process removes all of the trench fill dielectric material from over the CMP stop layer and does not remove any of the semiconductor material from the resistor head active areas and the resistor dummy active areas;

    removing a remaining portion of the CMP stop layer wherein the trench fill dielectric material in the STI trenches forms field oxide of the integrated circuit;

    implanting well dopants through the field oxide into the semiconductor material of the substrate under the field oxide in the area for the well resistor;

    heating the substrate in a well anneal process to activate the well dopants to form the well resistor; and

    forming contacts to provide electrical connections to the well resistor through the resistor head active areas, wherein the resistor dummy active areas are free of electrical connections above the substrate.

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