Semiconductor device with a thick bottom field plate trench having a single dielectric and angled sidewalls

• US 9,202,882 B2
• Filed: 05/01/2014
• Issued: 12/01/2015
• Est. Priority Date: 05/16/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Henson, Timothy D., Kelkar, Kapil, Radic, Ljubo
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US14/267,787
• Publication Number:
  US 20140339670A1
• Time in Patent Office: 579 Days
• Field of Search: 438/259, 438/270, 438/271, 438/589, 257/328, 257/330, 257/341
• US Class Current: 1/1
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Disclosed is a power device, such as a power MOSFET device and a method for fabricating same. The device includes a field plate trench. The field plate trench has a predetermined width and a predetermined sidewall angle. The device further includes a single trench dielectric on sidewalls of the field plate trench and at a bottom of the field plate trench. The single trench dielectric has a bottom thickness that is greater than a sidewall thickness. The device also includes a field plate situated within the single trench dielectric.

Claims

1. A power semiconductor device comprising:

a field plate trench, said field plate trench having a predetermined width and a predetermined sidewall angle, said predetermined sidewall angle being less than 85 degrees with respect to a bottom surface of said power semiconductor device;

a single trench dielectric situated inside said field plate trench, a bottom thickness of said single trench dielectric being determined by said predetermined width and said predetermined sidewall angle, said bottom thickness of said single trench dielectric being at least 120% greater than a sidewall thickness of said single trench dielectric;

a field plate situated within said single trench dielectric;

a gate trench situated laterally adjacent to said field plate trench, wherein a depth of said field plate trench is greater than that of said gate trench.

2. The power semiconductor device of claim 1, wherein said sidewall thickness of said single trench dielectric tapers from a bottom of a sidewall to a top of said sidewall.

3. The power semiconductor device of claim 1, wherein said single trench dielectric completely fills a bottom of said field plate trench.

4. The power semiconductor device of claim 1, wherein said predetermined sidewall angle is greater than 70 degrees with respect to said bottom surface of said power semiconductor device.

5. The power semiconductor device of claim 1, wherein said single trench dielectric comprises TEOS.

6. The power semiconductor device of claim 1, wherein a bottom portion of said field plate is pointed.

7. The power semiconductor device of claim 1, wherein said field plate trench is formed in a semiconductor substrate.

8. The power semiconductor device of claim 7, wherein said semiconductor substrate is an N type silicon substrate.

9. The power semiconductor device of claim 7, wherein said semiconductor substrate is a P type silicon substrate.

10. The power semiconductor device of claim 1, further comprising a source electrode, or a body junction.

11. A method of fabricating a power semiconductor device, said method comprising:

predetermining a bottom thickness of a single trench dielectric to form a field plate trench;

predetermining a sidewall angle of said field plate trench and a width of said field plate trench such that a later depositing of said single trench dielectric creates said bottom thickness of said single trench dielectric;

forming said field plate trench in a semiconductor substrate;

depositing said single trench dielectric into said field plate trench;

forming a gate trench laterally adjacent to said field plate trench, wherein a depth of said field plate trench is greater than that of said gate trench.

12. The method of claim 11, wherein said bottom thickness is greater than a sidewall thickness of said single trench dielectric.

13. The method of claim 12, wherein said bottom thickness is at least 120% greater than said sidewall thickness.

14. The method of claim 11, further comprising forming a field plate within said single trench dielectric.

15. The method of claim 11, wherein sidewalls of said field plate trench are at an angle of no less than 70 degrees and no more than 85 degrees with respect to a bottom surface of said power semiconductor device.

16. The method claim 11, wherein said single trench dielectric completely fills a bottom of said field plate trench.

17. The method of claim 11, wherein a sidewall thickness of said single trench dielectric tapers from a bottom of a sidewall to a top of said sidewall.

18. The method of claim 11, wherein said single trench dielectric comprises TEOS.

19. The method of claim 11, wherein said semiconductor substrate is an N type silicon substrate.

20. The method of claim 11, wherein said semiconductor substrate is a P type silicon substrate.