Method for manufacturing semiconductor structure

• US 9,202,913 B2
• Filed: 02/25/2011
• Issued: 12/01/2015
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Zhu, Huilong
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US13/133,120
• Publication Number:
  US 20120083106A1
• Time in Patent Office: 1,740 Days
• Field of Search: 438/227, 257/E21.453, 257/E21.635, 257/E21.623, 257/E21.458
• US Class Current: 1/1
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of the p-type field effect transistor; and d) performing annealing, so as to achieve the object of memorizing compressive stress in a channel of a transistor and improving the performance of the transistor. The method according to the present invention memorizes the compressive stress in the channel of the transistor by a stress memorization technique, increases mobility of holes, and improves overall performance of the semiconductor structure.

Claims

1. A method for manufacturing a semiconductor structure, comprising:

a) providing a p-type field effect transistor comprising source and drain regions;

b) forming a tensile-stressed layer on the p-type field effect transistor;

c) removing a portion of the tensile-stressed layer so that the remaining portion of the tensile-stressed layer has edges between the p-type field effect transistor and shallow trench isolations, and generating compressive stress in the channel of the p-type field effect transistor by the remaining portion of the tensile-stressed layer on the p-type field effect transistor;

d) performing annealing to memorize the compressive stress in the channel of the p-type field effect transistor; and

e) removing the remaining portion of the tensile-stressed layer after the annealing.

2. The method according to claim 1, wherein the tensile-stressed layer comprises at least one selected from a group including Si3N4, SiO2, SiOF, SiCOH, SiCO, SiCON, SiON, PSG and BPSG.

3. The method according to claim 1, wherein in step b), the tensile-stressed layer is formed by a deposition process.

4. The method according to claim 1, wherein in step c), the portion of the tensile-stressed layer is removed by selective etching.

5. The method according to claim 1, wherein after step a) and before step b), an etching stop layer is formed by a deposition process.

6. The method according to claim 5, wherein the etching stop layer is made of a material different from that of the tensile-stressed layer.

7. The method according to claim 6, wherein the etching stop layer comprises SiO2.

8. The method according to claim 4, wherein the step c) comprises:

forming a photoresist layer having a predetermined pattern by lithography; and

etching the tensile-stressed layer with the patterned photoresist layer as a mask.

9. The method according to claim 8, wherein after step c), the distance in the direction of the gate length between the edge of the remaining portion of the tensile-stressed layer and the external side of the gate is in the range of 0.02-0.2 μ

m.

10. The method according to claim 1, wherein the p-type field effect transistor comprises a dummy gate having a dummy gate conductor and a gate dielectric.

11. The method according to claim 10, wherein after step d), the method further comprises a step e) of:

removing the dummy gate conductor to provide an opening, and forming a gate in the opening.

12. The method according to claim 11, wherein in step e), the dummy gate conductor is removed by an etching process so as to expose the gate dielectric below the dummy gate conductor.

13. The method according to claim 11, wherein in step e), the dummy gate conductor and the gate dielectric are removed by an etching process so as to expose a substrate beneath the gate dielectric.