Latch-up free vertical TVS diode array structure using trench isolation

• US 9,202,938 B2
• Filed: 06/08/2013
• Issued: 12/01/2015
• Est. Priority Date: 11/30/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur
• Primary Examiner(s): HUBER, ROBERT T
• Application Number:
  US13/913,384
• Publication Number:
  US 20140363930A1
• Time in Patent Office: 906 Days
• Field of Search: 257/E27.038, 257/E27.039, 438/133, 438/328, 438/359
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0744 without components of the field effect type
• CPC Class Codes: H01L 27/075 Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
• CPC Class Codes: H01L 27/0755 Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0761 Vertical bipolar transistor in combination with diodes only
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/7416 the device being an antiparallel diode, e.g. RCT shorted anode structures enabling reverse conduction H01L29/0834
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/866 Zener diodes

Abstract

A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.

Claims

1. A method for manufacturing a transient voltage suppressing (TVS) array comprising:

opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate to form a first, second, third, fourth, and fifth semiconductor regions separated by said isolation trenches;

doping a body region having a second conductivity type in an upper part of said epitaxial layer with the body region extends laterally over an entire length of the first semiconductor region between two of the isolation trenches;

implanting a plurality of doped regions of said first conductivity type the semiconductor regions including a top doped region of the first conductivity type disposed under a top surface of the substrate encompassed in said body region and extends laterally over substantially an entire length of the first semiconductor region to constitute a bipolar transistor comprising two vertically stacked PN junctions disposed between the isolation trenches for triggering the bipolar transistor by a Zener diode comprising a bottom vertically stacked PN junction between the body region and the epitaxial layer for carrying a transient current for suppressing a transient voltage wherein the step of implanting the doped regions of the first conductivity type further implanting dopant regions of the first conductivity type interfacing with the body region as a first and a second low side diodes in the second and third semiconductor regions to work with the Zener diode as part of the TVS array;

implanting dopant regions of the second conductivity type in the fourth and fifth semiconductor regions wherein the dopant regions of the second conductivity type interface with the epitaxial layer of the first conductivity type as a first high side diode and a second high side diode respectively for the TVS array; and

filling the isolation trenches with an isolation trench material to prevent a latch-up of parasitic transistors inherently formed between multiple PN junctions in the TVS array.

2. The method of claim 1 further comprising:

forming a first I/O pad by depositing and patterning a metal layer on top of the semiconductor substrate to electrically connect with the first high side and first low side diodes and forming a second I/O pad by depositing and patterning the metal layer on top of the semiconductor substrate to electrically connect with the second high side and second low side diodes.

3. The method of claim 1 further comprising:

implanting doped regions of the second conductivity type away from the body region for forming the first and second high side diodes with said epitaxial layer to connect to said low side diodes encompassed in said body region with a first and a second input-output (IO) contact pads across said isolation trenches.

4. The method of claim 1 wherein:

said step of implanting a plurality of doped regions of the first conductivity type further comprising a step of forming a Zener doped region with a greater width wherein said Zener doped region comprising vertically stacked PN junctions in the first semiconductor region for functioning as a Zener diode with said body region in said epitaxial layer.

5. The method of claim 1 wherein:

said step opening a plurality of isolation trenches further comprising a step of opening isolation trenches or the first semiconductor region immediately next to said Zener diode for isolating said Zener diode for preventing said latch-up between said doped regions of different conductivity types.

6. The method of claim 1 further comprising:

depositing and patterning a metal layer on a bottom surface of said substrate to function as an electrode for said TVS array.

7. The method of claim 1 further comprising:

depositing a metal layer over said substrate and patterning said metal layer to function as a cathode to electrically connect the first low side diode to the second low side diode of the TVS array.

8. A method for manufacturing a transient voltage suppressing (TVS) array comprising:

opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate to separate a plurality of semiconductor regions separated by the isolation trenches;

doping a body region having a second conductivity type in an upper part of said epitaxial layer with the body region extends laterally over an entire length of a first semiconductor region between two of the isolation trenches;

implanting a plurality of doped regions of said first conductivity type in each of the semiconductor regions including a top doped region of the first conductivity type disposed under a top surface of the substrate encompassed in said body region and extends laterally over substantially an entire length of the first semiconductor region to constitute a bipolar transistor comprising vertically stacked PN junctions disposed between two of the isolation trenches for triggering the bipolar transistor by a Zener diode comprising a bottom vertically stacked PN junction between the body region and the epitaxial layer for carrying a transient current for suppressing a transient voltage wherein the step of implanting the doped regions of the first conductivity type further implanting dopant regions of the first conductivity type interfacing with the body region as a first low side diode and a second low side diode to work with the Zener diode as part of the TVS array;

implanting doped regions of the second conductivity type away from the body region for forming a first high side diode and a second high side diode with said epitaxial layer;

filling the isolation trenches with an isolation trench material; and

forming and patterning a top metal layer over the substrate in contact with the doped regions of the first conductivity type on top of the bipolar transistor constituting a cathode electrode and forming a bottom metal layer in contact with the semiconductor substrate constituting an anode electrode.

9. The method of claim 8 further comprising:

forming a first I/O pad by depositing and patterning the top metal layer to electrically connect the first high side diode and the first low side diode and forming a second I/O pad by depositing and patterning the top metal layer to electrically connect the second high side diode and the second low side diode.

10. The method of claim 9 further comprising:

implanting doped regions of the second conductivity type away from the body region for forming a first and a second high side diodes with said epitaxial layer to connect to a low side diode encompassed in said body region with a first and a second input-output (JO) contact pads across said isolation trenches.

11. The method of claim 8 wherein:

said step implanting a plurality of doped regions of the first conductivity type for forming a plurality of diodes further comprising a step of forming a Zener doped region with a greater width wherein said Zener doped region comprising vertically stacked PN junctions in the first semiconductor region for functioning as a Zener diode with said body region in said epitaxial layer.

12. The method of claim 8 further comprising:

depositing a metal layer patterning said metal layer to function as a cathode to electrically connect the first low side diode to the second low side diode of the TVS array.

13. The method of claim 8 wherein:

the step of implanting the doped region of the first conductivity type further comprising a step of implanting dopant regions of the first conductivity type interfacing with the body region as low side diodes in a second and a third semiconductor regions to work with the Zener diode as part of the TVS array.

14. The method of claim 8 wherein:

the step of implanting the doped region of the second conductivity type further comprises a step of implanting dopant regions of the second conductivity type in a fourth and a fifth semiconductor regions wherein the dopant regions of the second conductivity type interfaces with the epitaxial layer of the first conductivity type as the first and second high side diodes respectively for the TVS array.