Phase locked loop circuit

• US 9,203,418 B2
• Filed: 04/03/2014
• Issued: 12/01/2015
• Est. Priority Date: 05/14/2012
• Status: Expired due to Fees

• Current Assignee: Ensphere Solutions, Inc.
• Original Assignee: Ensphere Solutions, Inc.
• Inventors: Mohajeri, Hessam, Tourette, Bruno
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/244,400
• Publication Number:
  US 20140292388A1
• Time in Patent Office: 607 Days
• Field of Search: 327147-149, 327156-158
• US Class Current: 1/1
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/235 Nested phase locked loops

Abstract

The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Claims

1. A phase locked loop circuit, comprising an inner loop and an outer loop, wherein:

the inner loop comprises a frequency synthesizer locked on a master clock signal received from a master clock generator unit;

the outer loop comprises a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

2. The phase locked loop circuit of claim 1, wherein the inner loop and outer loop are fully digital or the phase locked loop is fully digital except the inner loop ring oscillator, charge pump and low-pass filter.

3. The phase locked loop circuit of claim 1, wherein a phase rotator followed by a divider connects an inner loop output and a binary phase detector input.

4. The phase locked loop circuit of claim 3, wherein:

the filter with proportional and integral action comprises an integrator correction accumulator and a proportional correction accumulator;

the proportional correction accumulator is configured to control the phase rotator;

the integrator correction accumulator is configured to integrate the phase detector output;

the integrator output goes through a gain stage K and further controls the sigma delta input.

5. The phase locked loop circuit of claim 4, wherein the gain stage K is configured to permit adjustments to the loop bandwidth and speed tracking.