Synchronized code recognition

• US 9,203,506 B2
• Filed: 10/16/2012
• Issued: 12/01/2015
• Est. Priority Date: 11/19/2004
• Status: Active Grant

• Current Assignee: Chemtron Research LLC (Intellectual Ventures LLC)
• Original Assignee: Chemtron Research LLC (Intellectual Ventures LLC)
• Inventors: Francis, Mark
• Primary Examiner(s): Ngo, Ricky
• Assistant Examiner(s): SAMUEL, DEWANDA A
• Application Number:
  US13/653,370
• Publication Number:
  US 20130039263A1
• Time in Patent Office: 1,141 Days
• Field of Search: 370/324, 370/315, 370/316
• US Class Current: 1/1
• CPC Class Codes: H04B 7/2126 using a reference station
• CPC Class Codes: H04W 56/0005 synchronizing of arrival of multiple uplinks
• CPC Class Codes: H04W 56/002 Mutual synchronization
• CPC Class Codes: H04W 56/0025 synchronizing potentially movable access points

Abstract

A system includes a central controller to transmit a plurality of synchronization codes through a transmission medium and a plurality of satellite controllers, each satellite controller configured to recognize one or more synchronization codes of the plurality of synchronization codes, each satellite controller comprising a synchronous clock signal generator to generate a synchronous clock signal each time the satellite controller recognizes the one or more synchronization codes of the plurality of synchronization codes.

Claims

1. A method, comprising:

recognizing, by a satellite controller including a synchronous clock signal generator and an internal clock signal generator, a first synchronization code of a plurality of synchronization codes transmitted from a central controller, wherein said recognizing comprises demodulating the first synchronization code and correlating the first synchronization code with a programmed code;

generating, by the synchronous clock signal generator, a synchronous clock signal in response to said recognizing by the satellite controller of the first synchronization code; and

generating, by the internal clock signal generator, an internal clock signal for the satellite controller based on a local clock signal received from a peripheral device associated with the satellite controller, wherein the internal clock signal is separate from the synchronous clock signal.

2. The method of claim 1, further comprising:

receiving, from the central controller, the plurality of synchronization codes through a transmission medium.

3. The method of claim 1, wherein the satellite controller is included in a first satellite controller group.

4. The method of claim 1, wherein the satellite controller further comprises a programmable timer communicatively coupled with the synchronous clock signal generator and the internal clock signal generator, and wherein the method further comprises triggering the programmable timer, by the synchronous clock signal, to be clocked by the internal clock signal and to time a response to the central controller.

5. The method of claim 4, wherein the satellite controller is included in a first satellite controller group, and wherein the method further comprises timing the response to the central controller to avoid interference with a response from another satellite controller in the first satellite controller group.

6. The method of claim 3, further comprising, by a satellite controller in a second satellite controller group:

recognizing a second synchronization code from the plurality of synchronization codes, wherein the second synchronization code is different from the first synchronization code; and

generating a second synchronous clock signal in response to the second synchronization code;

wherein the satellite controller in the second satellite controller group further comprises a programmable timer, and wherein the method further comprises triggering the programmable timer by the second synchronous clock signal.

7. The method of claim 6, further comprising timing a response to the central controller to avoid interference with a response from another satellite controller in the second satellite controller group or with a response from another satellite controller in the first satellite controller group.

8. The method of claim 1, wherein the first synchronization code is a periodic synchronization code, the method further comprising:

by a synchronous comparator communicatively coupled to the internal clock signal generator and to the synchronous clock signal generator;

accumulating a synchronous clock signal count by incrementing a synchronous clock signal count each time the first synchronization code is recognized; and

accumulating an internal clock signal count.

9. The method of claim 8, further comprising:

detecting, by the synchronous comparator, a difference between the synchronous clock signal count and the internal clock signal count;

generating an error signal when the difference between the synchronous clock signal count and the internal clock signal count exceeds a value; and

activating the peripheral device in response to the error signal.

10. The method of claim 9, wherein the peripheral device comprises a microcontroller.

11. The method of claim 9, wherein the peripheral device comprises a wireless transceiver.

12. The method of claim 9, wherein the peripheral device comprises a switch.

13. The method of claim 1, further comprising:

receiving, from the central controller, the plurality of synchronization codes through a wireless radio frequency medium.

21. The method of claim 1, wherein the first synchronization code is a periodic synchronization code, and wherein the synchronous clock signal is derived from the periodic synchronization code.

14. A method, comprising:

recognizing, by a satellite controller, one or more synchronization codes of a plurality of synchronization codes transmitted from a central controller;

generating, by a synchronous clock signal generator, a synchronous clock signal in response to recognition by the satellite controller of the one or more synchronization codes;

generating, by an internal clock signal generator, an internal clock signal for the satellite controller;

triggering a programmable timer with the synchronous clock signal, wherein the programmable timer is communicatively coupled with the synchronous clock signal generator and the internal clock signal generator;

clocking the programmable timer with the internal clock signal; and

switching a peripheral device, using the programmable timer, between a first state and a second state.

15. The method of claim 14, wherein the peripheral device comprises a microcontroller, and wherein the first state comprises an inactive state and the second state comprises an active state.

16. The method of claim 14, wherein the peripheral device comprises a wireless transceiver, and wherein the first state comprises an inactive state and the second state comprises an active state.

17. The method of claim 14, wherein the peripheral device comprises a switch.

18. A satellite controller, comprising:

a programmable correlator configured to;

cause the satellite controller to recognize one or more synchronization codes of a plurality of synchronization codes transmitted from a central controller by demodulating the one or more synchronization codes and correlating the one or more synchronization codes with a programmed code; and

generate a synchronous clock signal in response to the recognition by the satellite controller of the one or more synchronization codes; and

an internal clock signal generator configured to generate a separate internal clock signal for the satellite controller based on a local clock signal received from a peripheral device associated with the satellite controller.

19. The satellite controller of claim 18, further comprising a programmable timer, wherein the satellite controller is included in a satellite controller group, wherein a first synchronization code of the plurality of synchronization codes is configured to be recognized by satellite controllers in the satellite controller group, wherein the synchronous clock signal generator is further configured to generate the synchronous clock signal in response to the first synchronization code, and wherein the synchronous clock signal is configured to trigger the programmable timer.

20. A system, comprising:

a satellite controller configured to recognize one or more synchronization codes of a plurality of synchronization codes transmitted from a central controller;

a synchronous clock signal generator configured to generate a synchronous clock signal in response to recognition by the satellite controller of the one or more synchronization codes;

an internal clock signal generator configured to generate an internal clock signal for the satellite controller; and

a programmable timer communicatively coupled with the synchronous clock signal generator and the internal clock signal generator, wherein the programmable timer is configured to;

be triggered by the synchronous clock signal;

be clocked with the internal clock signal; and

switch a peripheral device between a first state and a second state depending on a detected difference between a synchronous clock signal count and an internal clock signal count.