Interconnect solder bumps for die testing

• US 9,207,275 B2
• Filed: 12/14/2012
• Issued: 12/08/2015
• Est. Priority Date: 12/14/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bartley, Gerald K., Germann, Philip R., Hovis, William P.
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): MCANDREW, CHRISTOPHER P
• Application Number:
  US13/715,225
• Publication Number:
  US 20140167808A1
• Time in Patent Office: 1,089 Days
• Field of Search: 324/762.03
• US Class Current: 1/1
• CPC Class Codes: G01R 31/26 Testing of individual semiconductor devices testing or measuring during manufacture or treatment H01L22/00; testing of photovoltaic devices H02S50/10
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2898 Sample preparation, e.g. removing encapsulation, etching sample preparation in general G01N1/00
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/11472 Profile of the lift-off mask
• CPC Class Codes: H01L 2224/1184 involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11906 with modification of the same mask
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]

Abstract

A semiconductor chip may include a die having one or more circuits. The semiconductor chip may include a plurality of die bumps, each having a first geometry, a first vertical profile, and a first volume. The die bumps may be coupled to the die and in electrical communication with the one or more circuits. The semiconductor device may include a plurality of test bumps each having a second geometry, a second vertical profile, and the first volume. The test bumps may be coupled to the die and in electrical communication with the one or more circuits. The first geometry and the second geometry may be adapted for the plurality of test bumps to make connection with a wafer probe to the test bumps without making a connection to any of the die bumps during a die test.

Claims

1. A semiconductor chip, comprising:

a die having one or more circuits;

a plurality of die bumps, each of the plurality of die bumps having a first geometry, each of the plurality of die bumps further having a first vertical profile, and each of the plurality of die bumps further having a first volume, the plurality of die bumps coupled to the die and in electrical communication with the one or more circuits, the first geometry adapted to prevent a wafer probe from connecting to the plurality of die bumps during a die test; and

a plurality of test bumps separate from the plurality of die bumps, each of the plurality of test bumps having a second geometry different from the first geometry, each of the plurality of test bumps further having a second vertical profile, and each of the plurality of test bumps further having the first volume, the plurality of test bumps coupled to the die and in electrical communication with the one or more circuits, the second geometry adapted to allow the wafer probe to connect to the plurality of test bumps during the die test.

2. The semiconductor chip of claim 1, wherein the second vertical profile of the test bumps is greater than the first vertical profile of the die bumps.

3. The semiconductor chip of claim 1, wherein the die bumps and the test bumps are made of a material that can be reflowed.

4. The semiconductor chip of claim 3, wherein the material is solder.

5. The semiconductor chip of claim 3, wherein the material is a tin-silver-copper (SAC) alloy.

6. The semiconductor chip of claim 1, wherein the test bumps and the die bumps have substantially the same pitch.

7. A semiconductor chip, comprising:

a die having one or more circuits;

a plurality of die bumps, each of the plurality of die bumps having a first geometry, each of the plurality of die bumps further having a first vertical profile, and each of the plurality of die bumps further having a first volume, the plurality of die bumps coupled to the die and in electrical communication with the one or more circuits; and

a plurality of test bumps separate from the plurality of die bumps, each of the plurality of test bumps having a second geometry different from the first geometry, each of the plurality of test bumps further having a second vertical profile, and each of the plurality of test bumps further having a second volume, the plurality of test bumps coupled to the die and in electrical communication with the one or more circuits, wherein the second vertical profile is greater than the first vertical profile.

8. The semiconductor chip of claim 7, wherein the first geometry and the second geometry are adapted for a wafer probe to make a connection to the test bumps without making a connection to any of the die bumps during a die test.

9. The semiconductor chip of claim 7, wherein the die bumps and the test bumps are made of a material that can be reflowed.

10. The semiconductor chip of claim 9, wherein the material is solder.

11. The semiconductor chip of claim 9, wherein the material is a tin-silver-copper (SAC) alloy.

12. The semiconductor chip of claim 7, wherein the test bumps and the die bumps have substantially the same pitch.

13. The semiconductor chip of claim 7, wherein the first volume and the second volume are substantially equal.

14. A method of testing a die of a semiconductor chip, comprising:

forming a plurality of die bumps to the die, each of the plurality of die bumps having a first geometry, each of the plurality of die bumps further having a first vertical profile, and each of the plurality of die bumps further having a first volume, the die having one or more circuits, the die bumps in electrical communication with the one or more circuits, the first geometry adapted to prevent a wafer probe from connecting to the plurality of die bumps during a die test;

forming a plurality of test bumps to the die, the plurality of test bumps separate from the plurality of die bumps, each of the plurality of test bumps having a second geometry, each of the plurality of test bumps further having a second vertical profile, and each of the plurality of test bumps further having the first volume, the test bumps in electrical communication with the one or more circuits, the second geometry adapted to allow the wafer probe to connect to the plurality of test bumps during the die test; and

testing the die at the plurality of test bumps with the wafer probe.

15. The method of claim 14, further comprising:

reflowing the test bumps and the die bumps to a third geometry.

16. The method of claim 15, further comprising:

coupling the semiconductor chip to an external circuit at the test bumps and die bumps.

17. The method of claim 14, wherein the second vertical profile of the test bumps is greater than the vertical profile of the die bumps.

18. The method of claim 14, wherein the forming the plurality of test bumps is completed by a die press process.

19. The method of claim 14, wherein the forming the plurality of test bumps is completed by a force compression process.