Dual core architecture of a control module of an engine
First Claim
Patent Images
1. A control system for a control module of a vehicle, comprising:
- a first integrated circuit (IC) core of a primary processor that generates a first control signal using first a central processing unit (CPU); and
a second IC core of said primary processor that generates a second control signal using a second CPU, and said second IC core generating a remedial control signal based on said first control signal and said second control signal, wherein said second IC core generates said second control signal in response to said second IC core receiving a notification signal from said first IC core indicating that said first IC core has generated said first control signal.
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Abstract
A control system for a control module of a vehicle includes a first integrated circuit (IC) core of a primary processor that generates a first control signal using a central processing unit (CPU). A second IC core of the primary processor generates a second control signal using a second CPU and generates a remedial control signal based on the first control signal and the second control signal.
34 Citations
19 Claims
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1. A control system for a control module of a vehicle, comprising:
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a first integrated circuit (IC) core of a primary processor that generates a first control signal using first a central processing unit (CPU); and a second IC core of said primary processor that generates a second control signal using a second CPU, and said second IC core generating a remedial control signal based on said first control signal and said second control signal, wherein said second IC core generates said second control signal in response to said second IC core receiving a notification signal from said first IC core indicating that said first IC core has generated said first control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for operating a control module of a vehicle, comprising:
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generating a first control signal using a first CPU of a first IC core on a primary processor; generating a second control signal using a second CPU of a second IC core on the primary processor in response to said second IC core receiving a notification signal from said first IC core indicating that said first IC core has generated said first control signal; and generating a remedial control signal using the second IC core based on said first control signal and said second control signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification