System, method, and computer program product for bulk synchronous binary program translation and optimization

• US 9,207,919 B2
• Filed: 01/17/2014
• Issued: 12/08/2015
• Est. Priority Date: 01/17/2014
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Diamos, Gregory Frederick
• Primary Examiner(s): Wong, Don
• Assistant Examiner(s): Wu, Daxin
• Application Number:
  US14/158,749
• Publication Number:
  US 20150205586A1
• Time in Patent Office: 690 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/3644 by instrumenting at runtime
• CPC Class Codes: G06F 8/41 Compilation
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/45516 Runtime code conversion or optimisation

Abstract

A system, method, and computer program product are provided for. The method includes the steps of executing a block of translated binary instructions by multiple threads and gathering profiling data during execution of the block of translated binary instructions. The multiple threads are then synchronized at a barrier instruction associated with the block of translated binary instructions and the block of translated binary instructions is replaced with optimized binary instructions, where the optimized binary instructions are produced based on the profiling data.

Claims

1. A method comprising:

executing, on a parallel processor, a block of translated binary instructions by multiple threads;

gathering profiling data during execution of the block of translated binary instructions;

synchronizing the multiple threads at a barrier instruction associated with the block of translated binary instructions, wherein the barrier instruction specifies a barrier hierarchy level;

replacing the block of translated binary instructions with optimized binary instructions, wherein the optimized binary instructions are produced based on the profiling data;

determining a lower level barrier than the specified barrier hierarchy level is supported; and

comparing the optimized binary instructions with one or more versions of binary instructions for the block that are associated with different multiple threads.

2. The method of claim 1, further comprising executing a second block of translated binary instructions by at least one thread during the synchronizing of the multiple threads and the replacing of the block.

3. The method of claim 1, further comprising merging the optimized binary instructions with versions of binary instructions when the comparing indicates that the optimized binary instructions substantially match the one or more versions of binary instructions.

4. The method of claim 3, wherein the merging comprises copying the optimized binary instructions to a portion of memory corresponding to the specified barrier hierarchy level and removing the optimized binary instructions and the one or more versions of binary instructions for the block from a portion of memory corresponding to the lower level barrier.

5. The method of claim 1, further comprising, after the synchronizing, invalidating an instruction cache that is accessed by the multiple threads.

6. The method of claim 1, wherein the optimized binary instructions are produced by a thread executing on a second processor.

7. The method of claim 1, wherein the parallel processor is a graphics processing unit.

8. The method of claim 1, further comprising, prior to executing the block of translated binary instructions, generating an instance of the block of translated binary instructions by each of the multiple threads.

9. The method of claim 1, further comprising:

copying the block of translated binary instructions; and

producing the optimized binary instructions based on the profiling data and the translated binary instructions.

10. The method of claim 9, wherein the optimized binary instructions are produced during execution of the block of translated binary instructions.

11. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising

executing a block of translated binary instructions by multiple threads;

gathering profiling data during execution of the block of translated binary instructions;

synchronizing the multiple threads at a barrier instruction associated with the block of translated binary instructions, wherein the barrier instruction specifies a barrier hierarchy level;

replacing the block of translated binary instructions with optimized binary instructions, wherein the optimized binary instructions are produced based on the profiling data;

determining a lower level barrier than the specified barrier hierarchy level is supported; and

comparing the optimized binary instructions with one or more versions of binary instructions for the block that are associated with different multiple threads.

12. A system comprising:

a memory configured to store a block of translated binary instructions; and

a plurality of multithreaded processing units that are included within a parallel processor and are coupled to the memory and configured to;

execute the block of translated binary instructions by multiple threads;

gather profiling data during execution of the block of translated binary instructions;

synchronize the multiple threads at a barrier instruction associated with the block of translated binary instructions, wherein the barrier instruction specifies a barrier hierarchy level;

replace the block of translated binary instructions with optimized binary instructions, wherein the optimized binary instructions are produced based on the profiling data;

determine a lower level barrier than the specified barrier hierarchy level is supported; and

compare the optimized binary instructions with one or more versions of binary instructions for the block that are associated with different multiple threads.

13. The system of claim 12, wherein the plurality of processing cores are further configured to execute a second block of translated binary instructions by at least one thread during the synchronizing of the multiple threads and the replacing of the block.

14. The system of claim 12 , wherein the plurality of multithreaded processing unit are further configured to merge the optimized binary instructions with the one or more versions of binary instructions when the comparing indicates that the optimized binary instructions substantially match the one or more versions of binary instructions.

15. The system of claim 12, wherein the plurality of multithreaded processing units are further configured to invalidate an instruction cache that is accessed by the multiple threads after the multiple threads are synchronized.

16. The system of claim 12, further comprising a second processor that executes a thread to produce the optimized binary instructions.