Shared virtual memory management apparatus for providing cache-coherence

• US 9,208,088 B2
• Filed: 01/03/2013
• Issued: 12/08/2015
• Est. Priority Date: 01/03/2012
• Status: Active Grant

• Current Assignee: Seoul National University R&DB Foundation (Seoul National University)
• Original Assignee: Seoul National University R&DB Foundation (Seoul National University)
• Inventors: Lee, Jaejin, Kim, Junghyun
• Primary Examiner(s): GIARDINO JR, MARK A
• Application Number:
  US13/733,396
• Publication Number:
  US 20140040563A1
• Time in Patent Office: 1,069 Days
• Field of Search: 711/144, 711/147, 711/150
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/0882 Page mode
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/656 Address space sharing

Abstract

A shared virtual memory management apparatus for ensuring cache coherence. When two or more cores request write permission to the same virtual memory page, the shared virtual memory management apparatus allocates a physical memory page for the cores to change data in the allocated physical memory page. Thereafter, changed data is updated in an original physical memory page, and accordingly it is feasible to achieve data coherence in a multi-core hardware environment that does not provide cache coherence.

Claims

1. A shared virtual memory management apparatus for ensuring cache coherence, comprising:

a plurality of cores which do not have individually designated physical memories but have one shared physical memory;

a shared virtual memory manager configured to allocate a shared virtual memory page shared by a plurality of cores and to manage cores'"'"' access to the allocated shared virtual memory page;

a physical memory manager configured to allocate a physical memory page when the plurality of cores simultaneously access the allocated shared virtual memory page, and to update contents of the shared virtual memory page written by any of the cores in the allocated physical memory page of the shared physical memory; and

a memory mapper configured to, when the contents of the shared virtual memory page written by any of the plurality of cores are updated in the physical memory page allocated by the physical memory manager, map the updated physical memory page to the shared virtual memory page of another core that does not perform a write operation to the shared virtual memory page, wherein

the physical memory manager reflects accurately updated data to the physical memory page by setting the physical memory page to uncacheable in order to avoid data inconsistency which may be caused by update on a cache-line basis, and

wherein in response to the shared virtual memory page being changed by two cores at the same time, the physical memory manager allocates a new physical memory page for one core, and updates shared virtual memory page of another core in the new allocated physical memory page, and further allocates an additional physical memory page to be simultaneously updated with the contents of shared virtual memory page changed by each of the two cores and the two cores sequentially write the contents of shared virtual memory page updated in the physical memory pages, which have been previously allocated to the respective two cores, to the additionally allocated physical memory page at release point, thereby simultaneously updating the contents of shared virtual memory paged changed by each of the two cores.

2. The shared virtual memory management apparatus of claim 1, wherein the physical memory manager is configured to allocate a physical memory page when one core with write permission is accessing the allocated shared virtual memory page which has already been accessed by another core with write permission.

3. The shared virtual memory management apparatus of claim 2, wherein the physical memory manager is configured to update the allocated physical memory page with contents of the shared virtual memory page written by a core that has most recently performed a memory-unlock operation when it is determined that cores with memory unlocked are present.

4. The shared virtual memory management apparatus of claim 3, wherein the shared virtual memory manager is configured to, when the contents of the shared virtual memory page written by the core with memory unlocked is updated in the physical memory page, allow write permission access of another core to the same shared virtual memory page.

5. The shared virtual memory management apparatus of claim 3, wherein the physical memory manager is configured to, when there are a plurality of cores with memory unlocked, allocate physical memory pages to the respective cores with memory unlocked and update the corresponding physical memory pages allocated to the respective cores with contents of the shared virtual memory page written by each of the cores with memory unlocked.

6. The shared virtual memory management apparatus of claim 5, wherein the physical memory manager is configured to further allocate an additional physical memory page in which contents of the shared virtual memory page written by all cores with memory unlocked are to be updated simultaneously.

7. The shared virtual memory management apparatus of claim 6, wherein the physical memory manager is configured to ensure cache coherence by sequentially writing the contents of the shared virtual memory page written by each of the cores with memory unlocked in the additionally allocated physical memory page.

8. The shared virtual memory management apparatus of claim 7, wherein the physical memory manager is configured to update the contents written in the additionally allocated physical memory page for providing cache coherence in a physical memory page that is actually mapped to the shared virtual memory page.

9. A shared virtual memory management apparatus for ensuring cache coherence, comprising:

a shared physical memory;

a plurality of cores each configured to access the shared physical memory as its respective main memory;

a shared virtual memory manager configured to allocate a shared virtual memory page shared by a plurality of cores and to manage cores'"'"' access to the allocated shared virtual memory page;

a physical memory manager configured to allocate a physical memory page when the plurality of cores simultaneously access the allocated shared virtual memory page, and to update contents of the shared virtual memory page written by any of the cores in the allocated physical memory page of the shared physical memory; and

a memory mapper configured to, when the contents of the shared virtual memory page written by any of the plurality of cores are updated in the physical memory page allocated by the physical memory manager, map the updated physical memory page to the shared virtual memory page of another core that does not perform a write operation to the shared virtual memory page, wherein

the physical memory manager reflects accurately updated data to the physical memory page by setting the physical memory page to uncacheable in order to avoid data inconsistency which may be caused by update on a cache-line basis, and

wherein in response to the shared virtual memory page being changed by two cores at the same time, the physical memory manager allocates a new physical memory page for one core, and updates shared virtual memory page of another core in the new allocated physical memory page, and further allocates an additional physical memory page to be simultaneously updated with the contents of shared virtual memory page changed by each of the two cores and the two cores sequentially write the contents of shared virtual memory page updated in the physical memory pages, which have been previously allocated to the respective two cores, to the additionally allocated physical memory page at release point, thereby simultaneously updating the contents of shared virtual memory paged changed by each of the two cores.

10. The shared virtual memory management apparatus of claim 9, wherein the physical memory manager is configured to allocate a physical memory page when one core with write permission is accessing the allocated shared virtual memory page which has already been accessed by another core with write permission.

11. The shared virtual memory management apparatus of claim 10, wherein the physical memory manager is configured to update the allocated physical memory page with contents of the shared virtual memory page written by a core that has most recently performed a memory-unlock operation when it is determined that cores with memory unlocked are present.

12. The shared virtual memory management apparatus of claim 11, wherein the shared virtual memory manager is configured to, when the contents of the shared virtual memory page written by the core with memory unlocked is updated in the physical memory page, allow write permission access of another core to the same shared virtual memory page.

13. The shared virtual memory management apparatus of claim 11, wherein the physical memory manager is configured to, when there are a plurality of cores with memory unlocked, allocate physical memory pages to the respective cores with memory unlocked and update the corresponding physical memory pages allocated to the respective cores with contents of the shared virtual memory page written by each of the cores with memory unlocked.

14. The shared virtual memory management apparatus of claim 13, wherein the physical memory manager is configured to further allocate an additional physical memory page in which contents of the shared virtual memory page written by all cores with memory unlocked are to be updated simultaneously.

15. The shared virtual memory management apparatus of claim 14, wherein the physical memory manager is configured to ensure cache coherence by sequentially writing the contents of the shared virtual memory page written by each of the cores with memory unlocked in the additionally allocated physical memory page.

16. The shared virtual memory management apparatus of claim 15, wherein the physical memory manager is configured to update the contents written in the additionally allocated physical memory page for providing cache coherence in a physical memory page that is actually mapped to the shared virtual memory page.