Dynamic SMT in parallel database systems

• US 9,208,197 B2
• Filed: 10/21/2011
• Issued: 12/08/2015
• Est. Priority Date: 10/21/2011
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kashyap, Sujatha
• Primary Examiner(s): Park, Grace
• Application Number:
  US13/278,943
• Publication Number:
  US 20130103670A1
• Time in Patent Office: 1,509 Days
• Field of Search: 707/713
• US Class Current: 1/1
• CPC Class Codes: G06F 16/24532 of parallel queries
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A data management system receives a query. A query optimizer determines an access plan for the query. The access plan has a plurality of stages, where each stage may have a different degree of parallelism for processing threads executing the stage. The query optimizer determines a maximum degree of parallelism for the plurality of stages and reserves processor cores based on the maximum degree of parallelism. The data management system schedules threads on the reserved processor cores for a first stage of the access plan. The data management system changes simultaneous multi-threading (SMT) mode for the processor cores when a second stage of the access plan having a different degree of parallelism is executed.

Claims

1. A method comprising:

determining an access plan for a query, the access plan having a plurality of stages;

determining a maximum degree of parallelism for the plurality of stages, wherein the maximum degree of parallelism is the highest degree of parallelism used by any one stage of the access plan;

reserving processor cores from a set of processor cores in accordance with the maximum degree of parallelism and a maximum SMT mode, wherein the maximum SMT mode is the maximum number of simultaneous threads executable by any one processor core in the set of processor cores;

set an SMT mode for the reserved processor cores based on a first degree of parallelism determined for a first stage of the access plan;

scheduling, based on the SMT mode, a plurality of threads for the first stage of the access plan on the reserved processor cores;

changing, during processing of the access plan, the SMT mode in accordance with a second degree of parallelism determined for a second stage of the access plan, wherein the SMT mode is decreased in response to determining that the second degree of parallelism is less than the first degree of parallelism determined for the first stage of the access plan or increased in response to determining that the second degree of parallelism is greater than the first degree of parallelism determined for the first stage of the access plan; and

scheduling, based on the changed SMT mode, a plurality of threads for the second stage of the access plan on the reserved processor cores.

2. The method of claim 1, wherein the access plan specifies the SMT mode on the one or more of the reserved processor cores.

3. The method of claim 1, wherein the access plan specifies a rule or formula for determining the SMT mode on the one or more of the reserved processor cores.

4. The method of claim 1, wherein changing the SMT mode on one or more of the reserved processor cores comprises changing the SMT mode by a supervisor module.

5. The method of claim 1, wherein the SMT mode includes at least a four thread mode and a single thread mode.

6. The method of claim 1, wherein the first stage comprises a scan stage and the second stage comprises a join stage.

7. A computer program product for processing data queries, the computer program product comprising:

a computer readable storage medium having computer usable program code embodied therewith, the computer usable program code comprising a computer usable program code configured to;

determine an access plan for a query, the access plan having a plurality of stages;

determine a maximum degree of parallelism for the plurality of stages, wherein the maximum degree of parallelism is the highest degree of parallelism used by any one stage of the access plan;

reserve processor cores from a set of processor cores in accordance with the maximum degree of parallelism and a maximum SMT mode, wherein the maximum SMT mode is the maximum number of simultaneous threads executable by any one processor core in the set of processor cores;

set an SMT mode for the reserved processor cores based on a first degree of parallelism determined for a first stage of the access plan;

schedule, based on the SMT mode, a plurality of threads for the first stage of the access plan on the reserved processor cores;

change, during processing of the access plan, the SMT mode in accordance with a second degree of parallelism determined for a second stage of the access plan, wherein the SMT mode is decreased in response to determining that the second degree of parallelism is less than the first degree of parallelism determined for the first stage of the access plan or increased in response to determining that the second degree of parallelism is greater than the first degree of parallelism determined for the first stage of the access plan; and

schedule, based on the changed SMT mode, a plurality of threads for the second stage of the access plan on the reserved processor cores.

8. The computer program product of claim 7, wherein the access plan specifies the SMT mode on the one or more of the reserved processor cores.

9. The computer program product of claim 7, wherein the access plan specifies a rule or formula for determining the SMT mode on the one or more of the reserved processor cores.

10. The computer program product of claim 7, wherein the computer usable program code configured to change the SMT mode on one or more of the reserved processor cores comprises computer usable program code configured to change the SMT mode by a supervisor module.

11. The computer program product of claim 7, wherein the SMT mode includes at least a four thread mode and a single thread mode.

19. The apparatus of claim 7, wherein the access plan specifies a rule or formula for determining the SMT mode on the one or more of the reserved processor cores.

12. An apparatus comprising:

one or more processor cores; and

a computer readable storage medium having computer usable program code for the one or more processor cores embodied therewith, the computer usable program code comprising a computer usable program code configured to;

determine an access plan for a query, the access plan having a plurality of stages;

determine a maximum degree of parallelism for the plurality of stages, wherein the maximum degree of parallelism is the highest degree of parallelism used by any one stage of the access plan;

reserve processor cores from a set of processor cores in accordance with the maximum degree of parallelism and a maximum SMT mode, wherein the maximum SMT mode is the maximum number of simultaneous threads executable by any one processor core in the set of processor cores;

set an SMT mode for the reserved processor cores based on a first degree of parallelism determined for a first stage of the access plan;

schedule, based on the SMT mode, a plurality of threads for the first stage of the access plan on the reserved processor cores;

change, during processing of the access plan, the SMT mode in accordance with a second degree of parallelism determined for a second stage of the access plan, wherein the SMT mode is decreased in response to determining that the second degree of parallelism is less than the first degree of parallelism determined for the first stage of the access plan or increased in response to determining that the second degree of parallelism is greater than the first degree of parallelism determined for the first stage of the access plan; and

schedule, based on the changed SMT mode, a plurality of threads for the second stage of the access plan on the reserved processor cores.

13. The apparatus of claim 12, wherein the access plan specifies the SMT mode on the one or more of the reserved processor cores.

14. The apparatus of claim 12, wherein the access plan specifies a rule or formula for determining the SMT mode on the one or more of the reserved processor cores.

15. The apparatus of claim 12, wherein the computer usable program code configured to change the SMT mode on one or more of the reserved processor cores comprises computer usable program code configured to change the SMT mode by a supervisor module.

16. The apparatus of claim 12, wherein the SMT mode includes at least a four thread mode and a single thread mode.

17. An apparatus comprising:

one or more processor cores;

a data management system executable by the one or more processor cores and configured to receive a query;

a query optimizer for the data management system, the query optimizer executable by the one or more processor cores and configured to;

determine an access plan for the query, the access plan having a plurality of stages;

determine a maximum degree of parallelism for the plurality of stages, wherein the maximum degree of parallelism is the highest degree of parallelism used by any one stage of the access plan;

reserve processor cores from a set of processor cores in accordance with the maximum degree of parallelism and a maximum SMT mode, wherein the maximum SMT mode is the maximum number of simultaneous threads executable by any one processor core in the set of processor cores;

set an SMT mode for the reserved processor cores based on a first degree of parallelism determined for a first stage of the access plan;

schedule, based on the SMT mode, a plurality of threads for the first stage of the access plan on the reserved one or more processor cores;

change, during processing of the access plan, the SMT mode in accordance with a second degree of parallelism determined for a second stage of the access plan, wherein the SMT mode is decreased in response to determining that the second degree of parallelism is less than the first degree of parallelism determined for the first stage of the access plan or increased in response to determining that the second degree of parallelism is greater than the first degree of parallelism determined for the first stage of the access plan; and

schedule, based on the changed SMT mode, a plurality of threads for the second stage of the access plan on the reserved processor cores.

18. The apparatus of claim 17, wherein the access plan specifies the SMT mode on the one or more of the reserved processor cores.

20. The apparatus of claim 17, and further comprising a supervisor module configured to change the SMT mode in accordance with the current second degree of parallelism determined for the second stage of the access plan.

21. The apparatus of claim 17, wherein the SMT mode includes at least a four thread mode and a single thread mode.