Semiconductor memory device having an electrically floating body transistor

• US 9,208,840 B2
• Filed: 07/14/2014
• Issued: 12/08/2015
• Est. Priority Date: 10/04/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US14/330,083
• Publication Number:
  US 20140319621A1
• Time in Patent Office: 512 Days
• Field of Search: 365/189.011, 365/189.04, 365/149
• US Class Current: 1/1
• CPC Class Codes: G11C 11/04 using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

Claims

1. A semiconductor memory cell formed in a semiconductor, the semiconductor memory cell comprising:

a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type;

a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type,

wherein the floating body region is bounded on the sides by at least a first insulating region having a first thickness and a second insulating region having a second thickness, wherein the second thickness is greater than the first thickness; and

a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer.

2. The semiconductor memory cell of claim 1, wherein said memory cell further comprises a bit line region at said surface, the bit line region having the second conductivity type.

3. The semiconductor memory cell of claim 1, further comprising a first well region of the first conductivity type beneath the buried region.

4. The semiconductor memory cell of claim 1, wherein said buried region is adapted to receive electrical signals of different amplitude or polarity, and wherein said electrical signals depend on an operation of said semiconductor memory cell.

5. The semiconductor memory cell of claim 2, further comprising a single shared contact through which bit line regions of adjacent memory cells are coupled.

6. The semiconductor memory cell of claim 2, further comprising a common region through which bit line regions of adjacent cells are coupled, the common region having the second conductivity type.

7. An array of memory cells formed in a semiconductor, the array comprising:

a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein the rows of memory cells define a first direction and the columns of memory cells define a second direction, and each of said memory cells comprising;

a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;

a buried region located beneath the surface of the memory cell, the buried region having a second conductivity type; and

a gate region above the floating body region, where the gate region overlays two floating body regions in the first direction.

8. The array of semiconductor memory cells of claim 7, wherein each of said semiconductor memory cells further comprises a bit line region located in the floating body region and substantially exposed at said surface, the bit line region having the second conductivity type.

9. The array of semiconductor memory cells of claim 7, further comprising a plurality of source lines crossing the array in a first direction beneath said surface, wherein the plurality of source lines are coupled to said buried regions.

10. The array of semiconductor memory cells of claim 8, further comprising a plurality of bit lines crossing the array in a second direction substantially orthogonal to the first direction, wherein the plurality of bit lines are coupled at said surface to said bit line regions.

11. The array of semiconductor memory cells of claim 7, further comprising a plurality of word lines crossing the array in a first direction above said surface, wherein the plurality of word lines are coupled to said gate regions.

12. The array of semiconductor memory cells of claim 7, further comprising a first well region of the first conductivity type beneath the buried region.

13. An array of memory cells formed in a semiconductor, the array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and a plurality of columns wherein the rows of memory cells define a first direction and the columns of memory cells define a second direction, and each of said memory cells comprising;

a bipolar device having a floating base region, a first region, a second region, and a gate region wherein;

a state of said semiconductor memory cell is stored in said floating base region;

said first region is located at the surface of said floating base region;

said second region is located below said floating base region,

said second region is commonly connected to at least two of said semiconductor memory cells in said matrix; and

said gate region overlays two of said semiconductor memory cells along the column direction.

14. The array of semiconductor memory cells of claim 13, further comprising a plurality of source lines crossing the array in a first direction beneath said surface, wherein the plurality of source lines are coupled to said second regions.

15. The array of semiconductor memory cells of claim 13, further comprising a plurality of bit lines crossing the array in a second direction substantially orthogonal to the first direction, wherein the plurality of bit lines are coupled at said surface to said first regions.

16. The array of semiconductor memory cells of claim 13, further comprising a plurality of word lines crossing the array in a first direction above said surface, wherein the plurality of word lines are coupled to said gate regions.

17. The array of semiconductor memory cells of claim 13, further comprising a first well region of a first conductivity type beneath the buried region.

18. The array of semiconductor memory cells of claim 13, wherein each of said second regions is adapted to receive electrical signals of different amplitude or polarity, wherein the electrical signals depend on an operation of each of said memory cells.

19. The array of semiconductor memory cells of claim 18, wherein said electrical signal applied to said second region comprises a pulse.

20. The array of semiconductor memory cells of claim 18, wherein said electrical signal applied to said second region comprises a constant amplitude level.