Techniques for improving reliability and performance of partially written memory blocks in modern flash memory systems

• US 9,208,888 B1
• Filed: 06/27/2014
• Issued: 12/08/2015
• Est. Priority Date: 06/27/2014
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Wakchaure, Yogesh B., Madraswala, Aliasgar S., Gaewsky, Kristopher H., Srinivasan, Charan
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/318,572
• Publication Number:
  US 20150380095A1
• Time in Patent Office: 529 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.21
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Claims

1. An apparatus comprising:

a storage device to store a partial block number and a last wordline voltage value corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory; and

memory controller logic, coupled to the non-volatile memory, to cause application of a reduced voltage level to erased wordlines of the non-volatile memory during a read operation to the non-volatile memory based at least in part on the partial block number and the last wordline voltage value.

2. The apparatus of claim 1, wherein the non-volatile memory is to comprise the storage device.

3. The apparatus of claim 1, wherein the memory controller logic is to cause application of the reduced voltage level to the erased wordlines of the non-volatile memory during the read operation to the non-volatile memory in response to a determination that the read operation is directed at the partially programmed memory block.

4. The apparatus of claim 1, wherein the memory controller logic or system firmware is to update the partial block number and the last wordline voltage value.

5. The apparatus of claim 1, wherein the non-volatile memory is to comprise a NAND non-volatile memory or a NOR non-volatile memory.

6. The apparatus of claim 1, wherein one or more processor cores are coupled to the memory controller logic to access data stored in the non-volatile memory.

7. A computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:

store, in a storage device, a partial block number and a last wordline voltage value corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory; and

cause, at memory controller logic, application of a reduced voltage level to erased wordlines of the non-volatile memory during a read operation to the non-volatile memory based at least in part on the partial block number and the last wordline voltage value.

8. The computer-readable medium of claim 7, wherein the non-volatile memory is to comprise the storage device.

9. The computer-readable medium of claim 7, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the memory controller logic to cause application of the reduced voltage level to the erased wordlines of the non-volatile memory during the read operation to the non-volatile memory in response to a determination that the read operation is directed at the partially programmed memory block.

10. The computer-readable medium of claim 7, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the memory controller logic or system firmware to update the partial block number and the last wordline voltage value.

11. The computer-readable medium of claim 7, wherein the non-volatile memory is to comprise a NAND non-volatile memory or a NOR non-volatile memory.

12. The computer-readable medium of claim 7, wherein the processor comprises one or more processor cores coupled to the memory controller logic to access data stored in the non-volatile memory.