Semiconductor device and operating method of semiconductor device
First Claim
1. A semiconductor device, comprising:
- a plurality of stacked chips;
a reference through silicon via (TSV) set passing through the plurality of stacked chips;
a plurality of TSVs passing through the plurality of stacked chips;
a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference TSV set; and
a determination unit suitable for determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals,wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, andwherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs.
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Abstract
A semiconductor device includes a plurality of stacked chips, a reference through silicon via (TSV) set passing through the plurality of stacked chips, a plurality of TSVs passing through the plurality of stacked chips, a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference TSV set and a determination unit suitable for determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs.
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Citations
18 Claims
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1. A semiconductor device, comprising:
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a plurality of stacked chips; a reference through silicon via (TSV) set passing through the plurality of stacked chips; a plurality of TSVs passing through the plurality of stacked chips; a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference TSV set; and a determination unit suitable for determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An operating method of a semiconductor device comprising a plurality of stacked chips, a reference through silicon via (TSV) set passing through the plurality of stacked chips and a plurality of TSVs passing through the plurality of stacked chips, comprising:
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generating a reference delay information indicating an amount of delay of the reference TSV set; and determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification