HVMOS reliability evaluation using bulk resistances as indices

• US 9,209,098 B2
• Filed: 05/19/2011
• Issued: 12/08/2015
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chia-Chung, Huang, Chi-Feng, Lu, Tse-Hua
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): BROWN, LAMARR A
• Application Number:
  US13/111,730
• Publication Number:
  US 20120293191A1
• Time in Patent Office: 1,664 Days
• Field of Search: 324/762.09
• US Class Current: 1/1
• CPC Class Codes: G01R 27/08 Measuring resistance by measuring both voltage and current
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

Claims

1. A method comprising:

determining a bulk resistance of a high-voltage PMOS (HVPMOS) device, wherein the determining the bulk resistance comprises;

measuring a plurality of source-to-bulk voltages of the HVPMOS device using a tester;

measuring a plurality of source currents of the HVPMOS device corresponding to the plurality of source-to-bulk voltages;

calculating a plurality of candidate bulk resistances from the plurality of source-to-bulk voltages and the plurality of source currents; and

selecting the bulk resistance from the plurality of candidate bulk resistances, with the bulk resistance being calculated from a source-to-bulk voltage in a pre-determined range, with the source-to-bulk voltage being one of the plurality of source-to-bulk voltages;

determining a reference bulk resistance comprising;

forming a plurality of reference sample HVPMOS devices;

determining bulk resistances of the plurality of reference sample HVPMOS devices; and

measuring current gains β

of the reference sample HVPMOS devices, wherein the reference bulk resistance is determined as a bulk resistance of one of the reference sample HVPMOS devices having a current gain β

equal to 1; and

comparing the bulk resistance with the reference bulk resistance, wherein the HVPMOS device with the bulk resistance greater than the reference bulk resistance is determined as not reliable, and the HVPMOS device with the bulk resistance smaller than the reference bulk resistance is determined as reliable.

2. The method of claim 1, wherein the bulk resistance is substantially proportional to a ratio of a source-to-bulk voltage of the HVPMOS device to a respective bulk current of the HVPMOS device.

3. The method of claim 2, wherein the bulk resistance is equal to the ratio, and is calculated with the respective source-to-bulk voltage being in a range between about 0.7V and about 0.8V.

4. The method of claim 1 further comprising:

forming a plurality of HVPMOS devices in a same chip;

determining bulk resistances of the plurality of HVPMOS devices; and

comparing the bulk resistances with the reference bulk resistance, wherein HVPMOS devices with respective bulk resistances greater than the reference bulk resistance are determined as not reliable, and the HVPMOS devices with respective bulk resistances smaller than the reference bulk resistance are determined as reliable.

5. The method of claim 1 further comprising measuring an active-region-to-guard-ring spacing of the HVPMOS device, wherein the active-region-to-guard-ring spacing is a distance between an outer edge of an active region of the HVPMOS device and a nearest guard ring, wherein the active-region-to-guard-ring spacing is measured in a channel width direction of the HVPMOS device, and wherein the HVPMOS device with the active-region-to-guard-ring spacing greater than about 2 μ

m is determined as not reliable, and the HVPMOS device with the active-region-to-guard-ring spacing smaller than 2 μ

m is determined as reliable.

6. The method of claim 5 further comprising a step selected from the group consisting essentially of:

measuring an inner-GR-to-GR-spacing of the HVPMOS device, wherein the HVPMOS device with the inner-GR-to-GR-spacing greater than about 30 μ

m is determined as not reliable, and the HVPMOS device with the inner-GR-to-GR-spacing smaller than 30 μ

m is determined as reliable;

measuring an active-region-spacing of the HVPMOS device, wherein the HVPMOS device with the active-region-spacing greater than about 6 μ

m is determined as not reliable, and the HVPMOS device with the active-region-spacing spacing smaller than 6 μ

m is determined as reliable; and

measuring a width of an active region of the HVPMOS device, wherein the HVPMOS device with the width greater than about 10 μ

m is determined as not reliable, and the HVPMOS device with the with smaller than 10 μ

m is determined as reliable.

7. A method comprising:

forming a plurality of sample high-voltage PMOS (HVPMOS) devices, wherein active-region-to-guard-ring spacings of the plurality of sample HVPMOS devices are different from each other, and the active-region-to-guard-ring spacings range from smaller than 2 μ

m to about 50 μ

m;

finding among the plurality of sample HVPMOS devices a reference HVPMOS device by looking for the reference HVPMOS device having a current gain equal to about 1;

determining a reference bulk resistance of the reference HVPMOS device, wherein a parasitic lateral bipolar junction transistor (BJT) of the reference HVPMOS device has a current gain equal to about 1, and wherein the lateral BJT comprises a source, a drain, and a well region of the reference HVPMOS device as an emitter, a collector, and a base, respectively, wherein the determining the reference bulk resistance comprises;

forming a plurality of reference sample HVPMOS devices;

determining bulk resistances of the plurality of reference sample HVPMOS devices; and

measuring current gains β

of the plurality of reference sample HVPMOS devices, wherein the measuring the current gains β

comprises measuring source currents Is and bulk currents of the reference sample HVPMOS devices using a tester, wherein the reference bulk resistance is determined as a bulk resistance of one of the reference sample HVPMOS devices having a current gain β

equal to 1;

finding bulk resistances of a plurality of HVPMOS devices on a chip; and

comparing the bulk resistances with the reference bulk resistance, wherein;

portions of the plurality of HVPMOS devices with bulk resistances greater than the reference bulk resistance are determined as not reliable; and

portions of the plurality of HVPMOS devices with bulk resistances smaller than the reference bulk resistance are determined as reliable.

8. The method of claim 7, wherein the reference bulk resistance and the bulk resistances are obtained by:

applying source-to-bulk voltages to the respective reference HVPMOS device and the plurality of HVPMOS devices, with the source-to-bulk voltages being in a range between about 0.7V and about 0.8V;

measuring bulk currents of the respective reference HVPMOS device and the plurality of HVPMOS devices corresponding to the source-to-bulk voltages; and

dividing the source-to-bulk voltages by the respective bulk currents of the respective reference HVPMOS device and the plurality of HVPMOS devices.

9. A method comprising:

forming a plurality of sample high-voltage PMOS (HVPMOS) devices having different active-region-to-guard-ring spacings;

measuring source currents and bulk currents of the plurality of sample HVPMOS devices using testers;

calculating a plurality of current gains from the source currents and bulk currents, wherein each of the plurality of current gains belongs to one of the plurality of sample HVPMOS devices;

selecting from the plurality of current gains a reference current gain substantially equal to 1, wherein the reference current gain belongs to a reference HVPMOS device among the plurality of sample HVPMOS devices; and

calculating a bulk resistance of the reference HVPMOS device, and selecting the bulk resistance of the reference HVPMOS device as a reference bulk resistance.

10. The method of claim 9 further comprising:

determining a bulk resistance of an additional HVPMOS device; and

comparing the reference bulk reference with the bulk resistance of the additional HVPMOS device.

11. The method of claim 10, wherein the additional HVPMOS device with the bulk resistance greater than the reference bulk resistance is determined as not reliable, and the additional HVPMOS device with the bulk resistance smaller than the reference bulk resistance is determined as reliable.

12. The method of claim 9, wherein the active-region-to-guard-ring spacings are distances from outer edges of active regions of the plurality of sample HVPMOS devices to respective nearest guard rings.

13. The method of claim 9, wherein the reference bulk resistance is obtained by dividing a source-to-bulk voltage by respective bulk currents of the reference HVPMOS device, and wherein the source-to-bulk voltage is in a range between about 0.7V and about 0.8V.