Hybrid carbon-metal interconnect structures

• US 9,209,136 B2
• Filed: 04/01/2013
• Issued: 12/08/2015
• Est. Priority Date: 04/01/2013
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Barth, Hans-Joachim
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US13/854,449
• Publication Number:
  US 20140291819A1
• Time in Patent Office: 981 Days
• Field of Search: 257/29, 257/40, 257/642, 257/E51.001, 257/E51.024, 257/E51.025, 257/614, 257/659, 257/751, 257/24, 257/E29.245, 257/E29.409, 257/E29.273, 257/E21.09, 257/E29.082, 438/151
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49872 : the conductive materials containing semiconductor material
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 : Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 : Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53276 : containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 29/1606 : Graphene
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H10K 85/221 : Carbon nanotubes

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.

Claims

1. An apparatus comprising:

a substrate;

a metal interconnect layer disposed on and in direct contact with the substrate and to serve as a growth initiation layer for a graphene layer; and

the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer to route electrical signals;

a first dielectric layer disposed on the graphene layer, the first dielectric layer in direct contact with the graphene layer and to protect the graphene layer during a deposition of a second dielectric layer that uses oxygen plasma, radicals or ions in the deposition;

the second dielectric layer disposed on the first dielectric layer, the second dielectric layer being in direct contact with the first dielectric layer,

wherein the first dielectric layer and the second dielectric layer are composed of one or more of silicon oxide, silicon carbide, silicon carbon nitride, or silicon nitride; and

the metal interconnect layer has a (111) texture; and

a photosensitive material disposed on and in direct contact with the second dielectric layer.

2. The apparatus of claim 1, wherein the graphene layer includes one or more mono-layers of graphene nanoribbons (GNRs).

3. The apparatus of claim 1, further comprising:

an interposer including the substrate,

wherein;

the substrate is composed of one or more of a semiconductor, glass, or metal;

the substrate does not include any active transistor devices formed on the substrate;

the metal interconnect layer is composed of copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), or palladium (Pd); and

the metal interconnect layer and the graphene layer are to route the electrical signals through the interposer.

4. The apparatus of claim 1, wherein material of the graphene layer is disposed on a top surface of the metal interconnect layer.

5. The apparatus of claim 1, wherein the metal interconnect layer and the graphene layer form a line structure, the apparatus further comprising:

a via structure, wherein electrically conductive material of the via structure terminates in the graphene layer.

6. The apparatus of claim 1, wherein the substrate includes one or more passive electronic devices and does not include any active electronic devices.

7. A system comprising:

an interposer including a substrate, a metal interconnect layer disposed on and in direct contact with the substrate and to serve as a growth initiation layer for a graphene layer, and the graphene layer, the graphene layer is formed directly on the metal interconnect layer; and

a die electrically coupled with the interposer, wherein the metal interconnect layer and the graphene layer are to route electrical signals of the die through the interposer;

a first dielectric layer disposed on the graphene layer, the first dielectric layer in direct contact with the graphene layer and to protect the graphene layer during a deposition of a second dielectric layer that uses oxygen plasma, radicals or ions in the deposition;

the second dielectric layer disposed on the first dielectric layer, the second dielectric layer being in direct contact with the first dielectric layer,

wherein the first dielectric layer and the second dielectric layer are composed of one or more of silicon oxide, silicon carbide, silicon carbon nitride, or silicon nitride; and

the metal interconnect layer has a (111) texture; and

a photosensitive material disposed on and in direct contact with the second dielectric layer.

8. The system of claim 7, further comprising:

a circuit board, wherein the interposer is electrically coupled with the circuit board and the circuit board is to route the electrical signals of the die; and

one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board, wherein the system is one of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.

9. The system of claim 7, wherein the substrate includes one or more passive electronic devices and does not include any active electronic devices.