Package-on-package structures

• US 9,209,163 B2
• Filed: 08/13/2012
• Issued: 12/08/2015
• Est. Priority Date: 08/19/2011
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Kao, Huahung, Liou, Shiann-Ming
• Primary Examiner(s): Diallo, Mamadou
• Assistant Examiner(s): Sylvia, Christina
• Application Number:
  US13/584,027
• Publication Number:
  US 20130043587A1
• Time in Patent Office: 1,212 Days
• Field of Search: 257/738, 257/686, 257/723, 257/E21.03, 257/E25.006, 257/E25.013, 257/E25.021, 257/E25.027
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73215 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/04 : Structure, shape, material or disposition of the bonding areas prior to the connecting process
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1438 : Flash memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Claims

1. A package on package arrangement comprising:

a first package including

a substrate layer including (i) a top side, and (ii) a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface;

a die coupled to the bottom side of the substrate layer;

an encapsulant covering the die;

a ball grid array (BGA) of first solder balls in recesses of the encapsulant; and

second solder balls melted by a non-weld process to the first solder balls in the recesses of the encapsulant, wherein the second solder balls (i) are partially in the recesses of the encapsulant and (ii) partially protrude beyond the encapsulant, wherein the portion of the second solder balls that protrudes beyond the encapsulant is substantially spherical, smooth, and void of any sharp features; and

a second package including

a plurality of rows of third solder balls that extend (i) across the substantially flat surface of the top side of the substrate layer of the first package and (ii) over the die coupled to the bottom side of the substrate layer of the first package, wherein the second package is attached, via the plurality of rows of third solder balls, to the substantially flat surface of the top side of the substrate layer of the first package.

2. The package on package arrangement of claim 1, further comprising:

an adhesive layer located between the die and the substrate layer,

wherein the adhesive layer attaches the die to the bottom side of the substrate layer of the first package.

3. The package on package arrangement of claim 1, further comprising:

a bond pad located on the bottom side of the die; and

a substrate pad located on the bottom side of the substrate layer of the first package,

wherein the bond pad of the die is coupled, via a wire, to the substrate pad of the substrate layer to route electrical signals of the die.

4. The package on package arrangement of claim 1, wherein:

the substrate layer comprises a first substrate layer;

the second package comprises a first die arranged next to a second die; and

each of the first die and the second die is connected to a second substrate layer in the second package via fourth solder balls.

5. The package on package arrangement of claim 4, wherein at least some of the plurality of rows of third solder balls are between (i) the first die and the second die of the second package and (ii) the die coupled to the bottom side of the substrate layer.

6. The package on package arrangement of claim 1, further comprising:

thermal interface material attached to a bottom side of the die.

7. The package on package arrangement of claim 6, further comprising:

thermal conductive material attached to the thermal interface material.

8. The package on package arrangement of claim 7, wherein the thermal interface material comprises one of a film, a grease composition, or an underfill material.

9. The package on package arrangement of claim 1, further comprising:

fourth solder balls attached to the bottom side of the substrate layer and a top side of the die; and

a plurality of through-silicon vias located in the die, wherein the plurality of through-silicon vias respectively extend between (i) at least some of the fourth solder balls and (ii) a plurality of fifth solder balls that are attached to a bottom side of the bottom package.

10. A stackable semiconductor package comprising:

a first package including

a substrate layer including (i) a top side, and (ii) a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface;

a die coupled to the bottom side of the substrate layer;

an encapsulant covering the die;

a ball grid array (BGA) of first solder balls in recesses of the encapsulant;

second solder balls melted to the first solder balls in the recesses of the encapsulant, wherein the second solder balls (i) are partially in the recesses of the encapsulant and (ii) partially protrude beyond the encapsulant by a first distance; and

third solder balls (i) electrically connected to the die via an interposer and (ii) protruding beyond the encapsulant by a second distance equal to the first distance; and

a second package including

a plurality of rows of fourth solder balls that extend (i) across the substantially flat surface of the top side of the substrate layer of the first package and (ii) over the die coupled to the bottom side of the substrate layer of the first package, wherein the second package is attached, via the plurality of rows of fourth solder balls, to the substantially flat surface of the top side of the substrate layer of the first package.

11. The package on package arrangement of claim 10, further comprising:

an adhesive layer located between the die and the substrate layer,

wherein the adhesive layer attaches the die to the bottom side of the substrate layer of the first package.

12. The package on package arrangement of claim 10, further comprising:

a bond pad located on the bottom side of the die; and

a substrate pad located on the bottom side of the substrate layer of the first package,

wherein the bond pad of the die is coupled, via a wire, to the substrate pad of the substrate layer to route electrical signals of the die.

13. The package on package arrangement of claim 10, wherein:

the substrate layer comprises a first substrate layer;

the second package comprises a first die arranged next to a second die; and

each of the first die and the second die is connected to a second substrate layer in the second package via fifth solder balls.

14. The package on package arrangement of claim 10, further comprising:

thermal interface material attached to a bottom side of the die.

15. The package on package arrangement of claim 14, further comprising:

thermal conductive material attached to the thermal interface material.

16. The package on package arrangement of claim 15, wherein the thermal interface material comprises one of a film, a grease composition, or an underfill material.

17. The package on package arrangement of claim 10, further comprising:

a printed circuit board attached to a bottom side of the die.

18. The package on package arrangement of claim 10, further comprising:

third solder balls attached to the bottom side of the substrate layer and a top side of the die; and

a plurality of through-silicon vias located in the die, wherein the plurality of through-silicon vias respectively extend between at least some of the third solder balls, and a plurality of fourth solder balls that are attached to a bottom side of the bottom package.

19. The package on package arrangement of claim 10, further comprising:

fifth solder balls attached to the bottom side of the substrate layer and a top side of the die.