Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices

• US 9,209,166 B2
• Filed: 03/23/2015
• Issued: 12/08/2015
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pratt, David S.
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US14/665,718
• Publication Number:
  US 20150194415A1
• Time in Patent Office: 260 Days
• Field of Search: 438/109, 438/118, 438/667, 257/686, 257/777, 257/E21.614
• US Class Current: 1/1
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16148 : the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/812 : Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releasably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.

Claims

1. A method of manufacturing semiconductor assemblies, comprising:

testing first dies of a wafer and individual second dies to determine known good first dies, known good second dies, known bad first dies, and known bad second dies; and

after testing the first dies and the second dies, attaching the individual known good second dies to each of the known good first dies of the wafer to form a plurality of known good stacked assemblies, and attaching the individual known bad second dies to each of the known bad first dies of the wafer to form a plurality of known bad stacked assemblies.

2. The method of claim 1, further comprising after forming the known good and known bad stacked assemblies, disposing encapsulant material in gaps between the second dies.

3. The method of claim 1, further comprising:

mounting the wafer to a temporary carrier; and

thinning the wafer to reduce heights of the first dies while the wafer is mounted on the temporary carrier and before attaching the second dies to the first dies.

4. The method of claim 3 wherein thinning the wafer includes removing material of the wafer so as to simultaneously expose a plurality of first die interconnects at a back side of the wafer that define external contacts for electrically coupling to contacts of the second dies.

5. The method of claim 1, further comprising cutting through the wafer to singulate the known good and known bad stacked assemblies.

6. The method of claim 1 wherein the individual second dies of the known good and known bad stacked assemblies include an integrated circuit and a terminal electrically coupled to corresponding first dies.

7. The method of claim 1 wherein each first die includes a first terminal, a first integrated circuit electrically coupled to the first terminal, and a first through die interconnect, wherein each second die includes a second terminal, a second integrated circuit electrically coupled to the second terminal, and a second through die interconnect, and wherein the second terminal is electrically coupled to the first through die interconnect.

8. A method of manufacturing microelectronic devices, comprising:

providing a wafer with a plurality of first dies that include known good first dies and known bad first dies; and

attaching separated second dies to each of the first dies to form a plurality of stacked good microelectronic devices and a plurality of stacked bad microelectronic devices, wherein the stacked good microelectronic devices include the known good first dies and known good second dies of the second dies, and wherein the stacked bad microelectronic devices include the known bad first dies and known bad second dies of the second dies.

9. The method of claim 8 wherein attaching the separated second dies to the first dies includes

mounting the known good second dies to the known good first dies of the wafer in a stacked configuration to form the stacked good microelectronic devices;

and

mounting the known bad second dies to the known bad first dies of the wafer in a stacked configuration to form the stacked bad microelectronic devices.

10. The method of claim 8, further comprising before attaching the second dies to the first dies, testing the first dies of the wafer and the second dies to identify the known good first dies, the known bad first dies, the known bad second dies, and the known bad second dies.

11. The method of claim 8, further comprising:

mounting the wafer to a temporary carrier; and

thinning the wafer to remove material from the first dies before attaching the second dies to the first dies.

12. The method of claim 11 wherein thinning the wafer includes removing material of the wafer so as to simultaneously expose a plurality of first die interconnects at a back side of the wafer that define external contacts which are subsequently electrically coupled to the second dies.

13. The method of claim 11 wherein after attaching the second dies to the first dies, the known good first dies individually comprise a first integrated circuit electrically coupled to a first terminal and a first through die interconnect, and wherein the known good second dies individually comprise a second terminal electrically coupled to a second integrated circuit, and wherein the second terminal is electrically coupled to the first through die interconnect such that the first through die interconnect is between positioned between the first terminal and the second terminal.

14. The method of claim 8, further comprising

disposing an underfill material between the wafer and the second dies, wherein the underfill material surrounds interconnect contacts between the wafer and the second dies;

and

thinning the second dies by removing material from the second dies and by removing at least some of the underfill material.

15. The method of claim 8, further comprising cutting through the wafer to singulate the stacked good microelectronic devices and the stacked bad microelectronic devices.

16. The method of claim 8, further comprising thinning the second dies after attaching the second dies to the first dies.

17. The method of claim 8, after attaching the second dies to the first dies, the method further comprising

disposing an encapsulating material between the second dies;

and

cutting through the encapsulating material and/or the second dies and through the wafer to singulate the stacked good and stacked bad microelectronic devices.