Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

• US 9,209,188 B2
• Filed: 03/04/2015
• Issued: 12/08/2015
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/637,688
• Publication Number:
  US 20150187776A1
• Time in Patent Office: 279 Days
• Field of Search: 365/185.05, 365/185.17
• US Class Current: 1/1
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said memory cell comprises;

a floating body region for storing data indicating a state of said memory cell; and

a back-bias region configured to inject charge into said floating body region to maintain said state of said memory cell;

wherein an amount of charge injected into said floating body is a function of a charge stored in said floating body region;

wherein said link or string comprises at least one contact configured to electrically connect said memory cells to at least one control line; and

wherein a number of said at least one contact is the same as or less than a number of said memory cells in said link or string.

2. The integrated circuit of claim 1, wherein said number of said at least one contact is less than said number of memory cells.

3. The integrated circuit of claim 1, where said semiconductor memory cells are connected in series.

4. The integrated circuit of claim 1, where said semiconductor memory cells are connected in parallel.

5. The integrated circuit of claim 1, where said integrated circuit is fabricated on a bulk silicon substrate.

6. The integrated circuit of claim 1, where said number of said at least one contact is two.

7. The integrated circuit of claim 1, wherein said memory cells further comprise first and second conductive regions interfacing with said floating body region.

8. The integrated circuit of claim 1, wherein each said memory cell further comprises a gate insulated from said floating body region.

9. The integrated circuit of claim 1, wherein at least one of said memory cells is a contactless memory cell.

10. The integrated circuit of claim 9, wherein a majority of said memory cells are contactless memory cells.

11. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said memory cell comprises a floating body region for storing data;

wherein said link or string comprises at least one contact configured to electrically connect said memory cells to at least one control line;

wherein a number of said at least one contact is the same as or less than a number of said memory cells in said link or string; and

wherein said at least one control line is connected to a read circuitry.

12. The integrated circuit of claim 11, wherein said number of said at least one contact is less than said number of said memory cells.

13. The integrated circuit of claim 11, where said semiconductor memory cells are connected in series.

14. The integrated circuit of claim 11, where said semiconductor memory cells are connected in parallel.

15. The integrated circuit of claim 11, where said integrated circuit is fabricated on a bulk silicon substrate.

16. The integrated circuit of claim 11, where said number of said at least one contact is two.

17. The integrated circuit of claim 11, wherein said memory cells further comprise first and second conductive regions interfacing with said floating body region.

18. The integrated circuit of claim 11, wherein each said memory cell further comprises a gate insulated from said floating body region.

19. The integrated circuit of claim 11, wherein at least one of said memory cells is a contactless memory cell.

20. The integrated circuit of claim 19, wherein a majority of said memory cells are contactless memory cells.