Self-aligned wrapped-around structure

• US 9,209,247 B2
• Filed: 05/10/2013
• Issued: 12/08/2015
• Est. Priority Date: 05/10/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre, Ching, Kuo-Cheng, Guo, Ta-Pen, Diaz, Carlos H.
• Primary Examiner(s): FERNANDES, ERROL V
• Application Number:
  US13/782,528
• Publication Number:
  US 20140332859A1
• Time in Patent Office: 942 Days
• Field of Search: 257/302, 257/329, 438/206, 438/156, 438/299
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first portion of the spacer, etching away an unprotected portion of the structure layer disposed outside a periphery collectively defined by the spacer and the photoresist to form a structure having a footer portion and a non-footer portion, the non-footer portion and the footer portion collectively encircling the semiconductor column, and removing the photoresist and the spacer.

Claims

1. A method of making a self-aligned vertical gate-all-around device, comprising:

forming a spacer around an exposed portion of a semiconductor column projecting from a gate layer;

forming a photoresist over a protected portion of the gate layer and a first portion of the spacer;

etching away an unprotected portion of the gate layer disposed outside a periphery collectively defined by the spacer and the photoresist to form a gate having a footer portion and a non-footer portion, the non-footer portion and the footer portion collectively encircling the semiconductor column; and

removing the photoresist and the spacer.

2. The method of claim 1, wherein the spacer is a hard mask spacer.

3. The method of claim 1, wherein the semiconductor column is a vertical column and the gate layer is a horizontal gate layer.

4. The method of claim 1, wherein the gate layer is a metal gate layer.

5. The method of claim 1, wherein the spacer has a spacer periphery that is at least partially arcuate.

6. The method of claim 1, wherein the spacer is formed in a shape of a ring.

7. The method of claim 1, further comprising forming the gate layer over an oxide layer and a semiconductor layer.

8. A method of making a self-aligned vertical gate-all-around device, comprising:

depositing a gate layer around an initial exposed portion of a semiconductor column and over an initial oxide layer;

forming an additional oxide layer over the gate layer and planarizing the additional oxide layer;

performing an etchback process to recess the additional oxide layer and a portion of the gate layer wrapped around the initially exposed portion of the semiconductor column;

forming a spacer around the gate layer remaining around the initially exposed portion of the semiconductor column and a subsequently exposed portion of the semiconductor column;

forming a photoresist over a protected portion of the gate layer and a first portion of the spacer;

etching away an unprotected portion of the gate layer disposed outside a periphery collectively defined by the spacer and the photoresist to form a gate having a footer portion and a non-footer portion, the footer portion and the non-footer portion collectively encircling the semiconductor column; and

removing the photoresist and the spacer.

9. The method of claim 8, further comprising planarazing the additional oxide layer using a chemical-mechanical polishing process.

10. The method of claim 8, further comprising defining a gate length by removing an upper portion of the gate layer using a chemical-mechanical polishing process and the etchback process.

11. The method of claim 8, wherein the semiconductor column is a vertical column and the gate layer is a horizontal gate layer.

12. The method of claim 8, wherein the gate layer is a metal gate layer.

13. The method of claim 8, wherein the spacer has a spacer periphery that is at least partially arcuate.

14. The method of claim 8, further comprising forming the gate layer over a silicon dioxide layer supported by a silicon substrate.

15. A method of making a self-aligned vertical gate-all-around device, comprising:

forming a gate layer over a substrate, the gate layer having a semiconductor feature protruding the gate layer;

forming a spacer around the semiconductor feature, the spacer covering a portion of the gate layer;

forming a patterned mask, the patterned mask covering a portion of the spacer and a portion of the gate layer;

patterning the gate layer to remove portions of the gate layer unprotected by one or more of the spacer and the patterned mask; and

removing the patterned mask.

16. The method of claim 15, further comprising:

forming a gate spacer over the gate layer, the gate spacer encircling a portion of the semiconductor feature, wherein the gate spacer is conductive;

wherein the forming the patterned mask comprises forming the spacer over the gate spacer.

17. The method of claim 16, wherein the forming the gate spacer comprises:

forming a gate spacer layer along sidewalls of the semiconductor feature;

forming a masking layer along sidewalls of the gate spacer layer; and

recessing the gate spacer layer, thereby forming the gate spacer.

18. The method of claim 17, wherein the forming the masking layer comprises:

forming the masking layer over an upper surface of the gate spacer layer;

planarizing the masking layer; and

recessing the masking layer.

19. The method of claim 15, wherein the spacer forms a ring encircling the semiconductor feature in a plan view.

20. The method of claim 15, wherein a portion of the spacer protrudes from the patterned mask.