Customized shield plate for a field effect transistor

• US 9,209,259 B2
• Filed: 03/04/2014
• Issued: 12/08/2015
• Est. Priority Date: 12/13/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mitra, Agni, Burdeaux, David C.
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Garcia, Joannie A
• Application Number:
  US14/196,611
• Publication Number:
  US 20140187012A1
• Time in Patent Office: 644 Days
• Field of Search: 438/304, 438/404, 438/405, 438/454, 438584-588, 438/595, 438/618, 438/621, 438/669, 438/682, 438/761, 438/763, 438/778, 438/FOR.163, 438/FOR.167, 438/FOR.168, 438/FOR.210, 438/FOR.349, 438/FOR.355, 438/FOR.428
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.

Claims

1. A semiconductor fabrication process, comprising:

depositing a shield interlevel dielectric (ILD) on a semiconductor wafer, the semiconductor wafer including a gate electrode overlying a gate dielectric overlying a semiconductor substrate, the semiconductor substrate comprising a channel region underlying the gate electrode laterally positioned between a drift region and a source region, the drift region positioned between the channel region and a drain region, wherein the gate electrode comprises a gate electrode of a lateral diffused metal oxide semiconductor transistor;

depositing a shield plate layer overlying the shield ILD;

patterning the shield plate layer to form a customized shield plate, the customized shield plate overlying a portion of the gate electrode and a portion of the drift region, the customized shield plate defining a customized shield plate edge, wherein a distance between the customized shield plate edge and a sidewall of the gate electrode proximal to the drain region varies along a length of the customized shield plate edge;

after patterning the shield plate layer, depositing a second shield plate layer overlying the shield ILD; and

patterning the second shield plate layer to form a second customized shield plate, the second customized shield plate overlying a portion of the gate electrode and a portion of the drift region, the second customized shield plate defining a second customized shield plate edge, wherein a distance between the second customized shield plate edge and the sidewall of the gate electrode proximal to the drain region varies along a length of the second customized shield plate edge.

2. The semiconductor fabrication process of claim 1, wherein the first shield plate is comprised of a first shield plate material and the second shield plate comprises a second shield plate material, wherein the first shield plate material differs from the second shield plate material.

3. A fabrication method, comprising:

obtaining a semiconductor substrate including a surface layer extending from an upper surface of an epitaxial layer to a surface depth;

forming a gate dielectric overlying a channel region of the surface layer;

forming a gate electrode overlying the gate dielectric, the gate electrode including a first sidewall and a second sidewall;

forming a channel region comprising a portion of the surface layer underlying the gate electrode;

forming a source region comprising a portion of the surface layer extending between the channel region and a source contact region;

forming a drift region comprising a portion of the surface layer extending between the channel region and a drain region;

forming a shield interlevel dielectric (ILD) overlying at least a portion of an upper surface of the gate electrode, the second sidewall, and a portion the drift region; and

forming a shield plate comprising an electrically conductive layer overlying at least a portion of the shield ILD, the shield plate defining a shield plate edge overlying the drift region, wherein the shield plate edge comprises a customized shield plate edge wherein a displacement between the customized shield plate edge and the second sidewall varies along a length of the second sidewall, and wherein the shield plate comprises a first shield plate, the shield plate edge comprises a first shield plate edge, and the shield ILD comprises a first shield ILD;

forming a second shield ILD including a portion overlying at least a portion of the upper surface of the gate electrode, the second sidewall, and a portion the drift region; and

forming a second shield plate comprising an electrically conductive layer overlying at least a portion of the second shield ILD, the second shield plate defining a second shield plate edge overlying the second shield ILD.

4. The method of claim 3, wherein the second shield plate edge defines a second customized shield plate edge overlying the drift region, wherein a displacement between the second shield plate edge and the second sidewall varies along a length of the second sidewall.

5. The method of claim 3, wherein the second shield plate defines a parallel shield plate edge wherein a displacement between the second shield plate edge and the second sidewall remains substantially constant along a length of the second sidewall.

6. The method of claim 5, wherein the second shield plate overlies the first shield plate.

7. The method of claim 6, wherein the first shield plate overlies the second shield plate.

8. The method of claim 3, wherein the second shield plate overlies the first shield plate.

9. The method of claim 8, wherein the displacement between the first shield plate edge and the second sidewall exceeds a displacement between the second shield plate edge and the second sidewall along a first portion of the first shield plate edge and wherein the displacement between the first shield plate edge and the second sidewall is less than a displacement between the second shield plate edge and the second sidewall along a second portion of the first shield plate edge.

10. The method of claim 3, wherein a thickness of the first shield ILD differs from a thickness of the second shield ILD.

11. The method of claim 3, wherein a thickness of the first shield plate differs from a thickness of the second shield plate.

12. The method of claim 3, wherein the first shield plate is comprised of a first shield plate material and the second shield plate comprises a second shield plate material, wherein the first shield plate material differs from the second shield plate material.

13. The method of claim 3, wherein the shield plate is comprised of a silicide.

14. The method of claim 3, wherein the shield plate edge comprises a plurality of line segments.

15. The method of claim 3, wherein the shield plate edge is configured to achieve a predetermined electrical characteristic of the shield plate.

16. A semiconductor fabrication process, comprising:

forming a shield interlevel dielectric (ILD) overlying at least a portion of an upper surface of a gate electrode, a sidewall of the gate electrode, and a portion a drift region extending between a channel region underlying the gate electrode and a drain region;

forming a shield plate comprising an electrically conductive layer overlying at least a portion of the shield ILD, the shield plate defining a shield plate edge overlying the drift region, wherein the shield plate edge comprises a customized shield plate edge wherein a displacement between the customized shield plate edge and a second sidewall varies along a length of the second sidewall;

forming a second shield ILD overlying at least a portion of the shield plate; and

forming a second shield plate overlying the second shield ILD.

17. The semiconductor fabrication process of claim 16, wherein the shield plate comprises silicide.