Semiconductor structure and method for manufacturing the same

• US 9,209,269 B2
• Filed: 12/01/2011
• Issued: 12/08/2015
• Est. Priority Date: 11/23/2011
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Inventors: Yin, Haizhou, Xu, Jing, Liu, Yunfei
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US14/354,884
• Publication Number:
  US 20150162415A1
• Time in Patent Office: 1,468 Days
• Field of Search: 257/347, 257/382, 257/734, 438/151, 438/655, 438/296, 438/662, 438/300
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A method for manufacturing a semiconductor structure comprises following steps: providing an SOI substrate, forming a gate stack on the SOI substrate, forming sidewall spacers on sidewalls of the gate stack, and forming source/drain regions on each side of the gate stack; depositing a first metal layer on surfaces of an entire semiconductor structure, and then removing the first metal layer; forming an amorphous semiconductor layer on surfaces of the source/drain regions; depositing a second metal layer on surfaces of the entire semiconductor structure, and then removing the second metal layer; and annealing the semiconductor structure. Accordingly, the present invention further provides a semiconductor structure. The present invention is capable of effectively reducing contact resistance at source/drain regions.

Claims

1. A method of manufacturing a semiconductor structure, comprising:

a) providing an SOI substrate, forming a gate stack on the SOI substrate, forming sidewall spacers on sidewalls of the gate stack, and forming source/drain regions on each side of the gate stack;

b) depositing a first metal layer on surfaces of the entire semiconductor structure, and then removing the first metal layer before any annealing, wherein some of the first metal layer has come into source/drain regions during formation of the first metal layer;

c) depositing an amorphous semiconductor layer to cover the semiconductor structure;

doping the amorphous semiconductor layer;

removing a part of the amorphous semiconductor layer, and keeping the amorphous semiconductor layer on surfaces of the source/drain regions;

d) depositing a second metal layer on surfaces of an entire semiconductor structure, and then removing the second metal layer before any annealing, wherein some of the second metal layer has come into the amorphous silicon layers after the second metal layer is removed;

e) annealing the semiconductor structure to form a first contact layer on surfaces of the source/drain regions and second contact layers are formed on the upper surface of each amorphous semiconductor layers on surfaces of the source/drain regions and some of the amorphous semiconductor layer remains between the first metal silicide layer and the second metal silicide layer after the annealing;

wherein step b) occurs before step c) and e).

2. The manufacturing method of claim 1, wherein the material of the first metal layer and/or the second metal layers comprises Ni or NiPt.

3. The manufacturing method of claim 1, wherein, the first contact layer and the second contact layers have a thickness of 2 nm.

4. The manufacturing method of claim 3, wherein the first contact layer and the second contact layers comprises NiSi.

5. The manufacturing method of claim 1, wherein the type of dopants is the same as the type of a semiconductor device intended to manufacture.

6. The method of claim 5, wherein the amorphous semiconductor layers on surfaces of the source/drain regions are amorphous Si layers.

7. The method of claim 5, wherein the amorphous semiconductor layers on surfaces of the source/drain regions have a thickness between 3 nm to 5 nm.