Vertical III-V nanowire field-effect transistor using nanosphere lithography

• US 9,209,271 B1
• Filed: 08/27/2015
• Issued: 12/08/2015
• Est. Priority Date: 08/22/2013
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Texas System (University of Texas System)
• Original Assignee: Board of Regents of the University of Texas System (University of Texas System)
• Inventors: Lee, Jack C., Xue, Fei
• Primary Examiner(s): Taylor, Earl
• Application Number:
  US14/837,258
• Publication Number:
  US 20150364572A1
• Time in Patent Office: 103 Days
• Field of Search: 438/156, 438/212, 257/210
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.

Claims

1. A method for fabricating a vertical III-V nanowire field-effect transistor, the method comprising:

depositing a first layer of doped III-V semiconductor material on a substrate of III-V semiconductor material;

depositing a layer of undoped III-V semiconductor material on top of said first layer of doped III-V semiconductor material;

depositing a second layer of doped III-V semiconductor material on top of said layer of undoped III-V semiconductor material;

growing a first dielectric layer on top of said second layer of doped III-V semiconductor material;

depositing self-assembled monolayers of nanospheres on said first dielectric layer; and

forming nanopillars using said nanospheres as a mask and said first dielectric layer as a hard mask to etch said second layer of doped III-V semiconductor material and said layer of undoped III-V semiconductor material using nanosphere lithography.

2. The method as recited in claim 1, wherein said first dielectric layer comprises silicon dioxide.

3. The method as recited in claim 1, wherein a diameter of said nanospheres is controlled via oxygen plasma.

4. The method as recited in claim 1 further comprising:

dry etching said nanospheres and said first dielectric layer to remove said nanospheres and said first dielectric layer.

5. The method as recited in claim 4 further comprising:

depositing a second dielectric layer over said nanopillars and a remaining portion of said first layer of doped III-V semiconductor material that is exposed following said dry etching.

6. The method as recited in claim 5 further comprising:

depositing a gate metal over said second dielectric layer; and

depositing a third dielectric layer over said gate metal.

7. The method as recited in claim 6 further comprising:

etching said third dielectric layer to expose said gate metal; and

etching a portion of said gate metal and a portion of said second dielectric layer to expose a top portion of said nanopillars.

8. The method as recited in claim 7 further comprising:

removing a remaining portion of said third dielectric layer to expose a portion of said gate metal;

depositing a fourth dielectric layer over said exposed nanopillars and said exposed gate metal; and

depositing a photoresist layer over a portion of said fourth dielectric layer.

9. The method as recited in claim 8 further comprising:

etching said fourth dielectric layer according to a pattern in said photoresist layer in order to form a drain contact; and

etching a portion of said fourth dielectric layer to form a gate contact.

10. The method as recited in claim 9 further comprising;

adding a source contact to a bottom of said substrate.