Integrated device having MOSFET cell array embedded with barrier Schottky diode

• US 9,209,293 B2
• Filed: 04/18/2013
• Issued: 12/08/2015
• Est. Priority Date: 12/20/2012
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Hung, Chien-Chung, Chen, Young-Shying, Yen, Cheng-Tyng, Lee, Chwan-Ying
• Primary Examiner(s): Miyoshi, Jesse Y
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US13/865,980
• Publication Number:
  US 20140175559A1
• Time in Patent Office: 964 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a plurality of MOS transistor cells and at least one JBS diode. Any two adjacent MOS transistor cells are separated by a separating line. A first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line. The JBS diode is disposed at an intersection region between the first separating line and the second separating line. The JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells.

Claims

1. An integrated device having a metal oxide semiconductor field effect transistor (MOSFET) cell array embedded with a junction barrier Schottky (JBS) diode, comprising a plurality of areas, each area comprising:

a plurality of MOS transistor cells, wherein any two adjacent MOS transistor cells are separated by a separating line, and wherein a first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line, wherein the MOS transistor cells of each area comprises a plurality of well regions of a second conductivity type, and any two adjacent well regions are separated by one of the separating lines;

a drift layer of the first conductivity type, disposed on a substrate, wherein the well regions are disposed in the drift layer;

at least one JBS diode, disposed in the drift layer at an intersection region between the first separating line and the second separating line, and overlapping with the well regions, wherein the JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells, wherein the at least one JBS diode comprises a plurality of first junction barrier regions of the second conductivity type, and the plurality of first junction barrier regions extend into corners of the well regions of the second conductivity type;

a plurality of source regions of a first conductivity type, disposed in the well regions;

a plurality of body regions of the second conductivity type, disposed in the middle of the source regions in the well regions;

a plurality of source contacts, disposed on and electrically connected to the body regions and a portion of the source regions;

a first anode contact, covering a portion of the first junction barrier regions and a portion of the drift layer and electrically connected to the source contacts and the first junction barrier regions; and

a cathode, disposed in the substrate below the drift layer.

2. The integrated device of claim 1, wherein the MOS transistor cells of each area further comprises:

a plurality of gates, respectively disposed on the separating lines and extending onto the adjacent well regions and the source regions.

3. The integrated device of claim 2, wherein the MOS transistor cells of each area further comprises:

a drain region of the first conductivity type, disposed in the substrate; and

a plurality of gate dielectric layers, disposed between the gates and the drift layer and between the gates and the well regions.

4. The integrated device of claim 3, wherein the gates further extend into the drift layer at the separating lines.

5. The integrated device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

6. The integrated device of claim 1, wherein the first junction barrier regions further extend to contact the source regions.

7. The integrated device of claim 1, wherein at least one of the first junction barrier regions extend into a single edge of one of the well regions.

8. The integrated device of claim 1, wherein at least one of the first junction barrier regions extend into multiple edges of one of the well regions.

9. The integrated device of claim 1, wherein the at least one JBS diode of each area further comprises:

a plurality of second junction barrier regions, disposed at edges of the well regions; and

a plurality of anode contact, covering a portion of the second junction barrier regions and a portion of the drift layer.

10. The integrated device of claim 1, wherein in each area, the plurality of MOS transistor cells comprises three MOS transistor cells.

11. The integrated device of claim 1, wherein in each area, the plurality of MOS transistor cells comprises four MOS transistor cells.

12. The integrated device of claim 1, wherein in each area, an area of the JBS diode is less than an area of each of the MOS transistor cells.

13. The integrated device of claim 1, wherein the MOS transistor cells comprise silicon carbide MOS transistor cells.

14. The integrated device of claim 1, wherein an area of the JBS diode is less than an area of each of the MOS transistor cells.

15. The integrated device of claim 14, wherein the area of the JBS diode is ¼

to ½

the area of each of the MOS transistor cells.

16. The integrated device of claim 1, wherein a plurality of upper surfaces of the well regions and a plurality of upper surfaces of the first junction barrier regions are coplanar.

17. The integrated device of claim 1, wherein a portion of a bottom surface of each first junction barrier region is not covered by an adjacent well region.