Semiconductor device and method for manufacturing the semiconductor device

• US 9,209,310 B2
• Filed: 10/06/2010
• Issued: 12/08/2015
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Nguyen, Hoan C
• Application Number:
  US12/899,276
• Publication Number:
  US 20110084270A1
• Time in Patent Office: 1,889 Days
• Field of Search: 349 42- 43
• US Class Current: 1/1
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to provide a thin film transistor including an oxide semiconductor layer, in which a material used for the oxide semiconductor layer and a material used for source and drain electrode layers are prevented from reacting with each other. The source and drain electrode layers provided over a substrate having an insulating surface have a stacked structure of two or more layers. In the stack of layers, a layer which is in contact with an oxide semiconductor layer is a metal layer including a metal element other than a metal element included in the oxide semiconductor layer. An element selected from Sn, Sb, Se, Te, Pd, Ag, Ni, and Cu; an alloy containing any of these elements as a component; an alloy containing any of these elements in combination; or the like is used for a material of the metal layer used.

Claims

1. A semiconductor device comprising:

a substrate having an insulating surface;

a gate electrode layer over the substrate having the insulating surface;

a gate insulating layer over the gate electrode layer;

a source electrode layer and a drain electrode layer over the gate insulating layer; and

an oxide semiconductor layer over the source electrode layer and the drain electrode layer,

wherein the source electrode layer and the drain electrode layer are formed with a stack comprising a first metal layer and a second metal layer,

wherein the first metal layer and the second metal layer are in contact with the oxide semiconductor layer,

wherein the first metal layer is formed using a metal layer of a metal element selected from Se and Te, an alloy containing any of these elements as a component, or an alloy containing any of these elements in combination,

wherein the first metal layer is between the oxide semiconductor layer and the second metal layer,

wherein the second metal layer is between the first metal layer and the gate insulating layer,

wherein the second metal layer is formed using a metal layer of a metal element selected from Al, Ti, Mo, and W, an alloy containing any of these elements as a component, or an alloy containing any of these elements in combination,

wherein a first edge of the first metal layer is aligned with an edge of the oxide semiconductor layer, and

wherein the oxide semiconductor layer is not in contact with a top surface of the second metal layer.

2. The semiconductor device according to claim 1, wherein an entire portion of the oxide semiconductor layer overlaps with the gate electrode layer in a channel length direction.

3. The semiconductor device according to claim 1, wherein a second edge of the first metal layer is aligned with an edge of the second metal layer.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

5. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming a stack comprising a first metal layer and a second metal layer over the gate insulating layer;

selectively etching the stack comprising the first metal layer and the second metal layer, so that a source electrode layer and a drain electrode layer having the stack are formed; and

forming an oxide semiconductor layer over the source electrode layer and the drain electrode layer,

selectively etching the oxide semiconductor layer and the first metal layer, so that a first edge of the first metal layer is aligned with an edge of the oxide semiconductor layer,

wherein a metal element included in the first metal layer is at least one selected from Se and Te,

wherein the first metal layer and the second metal layer are in contact with the oxide semiconductor layer,

wherein the first metal layer is between the oxide semiconductor layer and the second metal layer,

wherein the second metal layer is between the first metal layer and the gate insulating layer,

wherein a metal element included in the second metal layer is at least one selected from Al, Ti, Mo, and W, and

wherein the oxide semiconductor layer is not in contact with a top surface of the second metal layer.

6. The method for manufacturing the semiconductor device according to claim 5, wherein the metal element included in the first metal layer is other than a metal element included in the oxide semiconductor layer.

7. The method for manufacturing the semiconductor device according to claim 5, wherein an entire portion of the oxide semiconductor layer overlaps with the gate electrode layer in a channel length direction.

8. The method for manufacturing the semiconductor device according to claim 5, wherein a second edge of the first metal layer is aligned with an edge of the second metal layer.

9. The method for manufacturing the semiconductor device according to claim 5, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

10. A semiconductor device comprising:

a substrate having an insulating surface;

a gate electrode layer over the substrate having the insulating surface;

a gate insulating layer over the gate electrode layer;

a source electrode layer and a drain electrode layer over the gate insulating layer; and

an oxide semiconductor layer over the source electrode layer and the drain electrode layer,

wherein the source electrode layer and the drain electrode layer are formed with a stack comprising a first metal layer and a second metal layer,

wherein the first metal layer and the second metal layer are in contact with the oxide semiconductor layer,

wherein the first metal layer is formed using a metal layer of a metal element selected from Se and Te, an alloy containing any of these elements as a component, or an alloy containing any of these elements in combination,

wherein the metal element included in the first metal layer is different from a metal element included in the oxide semiconductor layer,

wherein the first metal layer is between the oxide semiconductor layer and the second metal layer,

wherein the second metal layer is between the first metal layer and the gate insulating layer,

wherein the second metal layer is formed using a metal layer of an element selected from Al, Ti, Mo, and W, an alloy containing any of these elements as a component, or an alloy containing any of these elements in combination,

wherein a first edge of the first metal layer is aligned with an edge of the oxide semiconductor layer, and

wherein the oxide semiconductor layer is not in contact with a top surface of the second metal layer.

11. The semiconductor device according to claim 10, wherein an entire portion of the oxide semiconductor layer overlaps with the gate electrode layer in a channel length direction.

12. The semiconductor device according to claim 10, wherein a second edge of the first metal layer is aligned with an edge of the second metal layer.

13. The semiconductor device according to claim 10, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.