Micro device with stabilization post

• US 9,209,348 B2
• Filed: 04/08/2015
• Issued: 12/08/2015
• Est. Priority Date: 07/08/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Hu, Hsin-Hua, Chang, Kevin K. C., Bibl, Andreas
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US14/681,715
• Publication Number:
  US 20150214420A1
• Time in Patent Office: 244 Days
• Field of Search: 257/13, 438/26
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A method and structure for stabilizing an array of micro devices is disclosed. A stabilization layer includes an array of stabilization cavities and array of stabilization posts. Each stabilization cavity includes sidewalls surrounding a stabilization post. The array of micro devices is on the array of stabilization posts. Each micro device in the array of micro devices includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Claims

1. A method of forming an array of micro devices comprising:

patterning a device layer to form an array of micro device mesa structures over a handle substrate;

forming a patterned sacrificial layer including an array of openings over the corresponding array of micro device mesa structures;

forming a stabilization layer over the patterned sacrificial layer and within the array of openings; and

removing the handle substrate.

2. The method of claim 1, wherein each micro device mesa structure includes a p-doped layer, an n-doped layer, and a quantum well layer between the p-doped layer and the n-doped layer.

3. The method of claim 2, further comprising:

forming the array of openings in the patterned sacrificial layer directly over an array of conductive contacts of the corresponding array of micro device mesa structures.

4. The method of claim 2, wherein the patterning the device layer to form the array of micro device mesa structures leaves unremoved portions of the device layer between the array of micro device mesa structures, and further comprising removing the unremoved portions of the device layer to form an array of laterally separate micro LED devices after removing the handle substrate.

5. The method of claim 4, wherein removing the unremoved portions of the device layer comprises thinning the array of micro device mesa structures so that an exposed top surface of the array of micro LED devices is below an exposed top surface of the patterned sacrificial layer between the micro LED devices.

6. The method of claim 1, further comprising bonding the stabilization layer to a carrier substrate prior to removing the handle substrate.

7. The method of claim 6, wherein bonding the stabilization layer to the carrier substrate comprises curing the stabilization layer.

8. The method of claim 1, further comprising removing the patterned sacrificial layer after removing the handle substrate.

9. The method of claim 1, wherein the stabilization layer is formed of a thermoset material.

10. The method of claim 1, wherein the array of openings are separated by a pitch of 1 μ

m to 10 μ

m.