Ratioless near-threshold level translator

• US 9,209,810 B2
• Filed: 04/16/2014
• Issued: 12/08/2015
• Est. Priority Date: 04/16/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Williams, Jacob T., Cunningham, Jeffrey C., Ramanan, Karthik
• Primary Examiner(s): Le, Dinh
• Application Number:
  US14/253,930
• Publication Number:
  US 20150303923A1
• Time in Patent Office: 601 Days
• Field of Search: 327/306, 327/333, 326 61- 62, 326 80- 81
• US Class Current: 1/1
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.

Claims

1. A circuit, comprising:

an output circuit (202, 302, 402) coupled between a first power supply terminal and a second power supply terminal that receives (IN1) a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal (VDD1) and a second logic state based on a voltage at the second power supply terminal (VSS1) and provides a second logic signal (IN2), complementary to the first logic signal, that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal; and

a level translator, comprising;

a first transistor (214, 314, 416) of a first conductivity type having a first current electrode for receiving the first logic signal, a second current electrode, and a control electrode;

a first transistor (208, 308, 422) of a second type having a first current electrode for receiving the first logic signal, a second current electrode coupled to the second current electrode of the first transistor of the first type, and a control electrode coupled to the second power supply terminal;

a second transistor (206, 304, 406) of the second conductivity type having a control electrode that receives the first input signal, a first current electrode coupled to a third power supply terminal (VDD2, VSS2), and a second current electrode as a first output;

a second transistor (212, 312, 412) of the first conductivity type having a control electrode for receiving the first logic signal;

a third transistor (210, 310, 410) of the first conductivity type having a control electrode coupled to the second current electrode of the second transistor of the second conductivity type, wherein first and second current electrodes of the second and third transistors of the first conductivity type are coupled in series between a fourth power supply terminal and the second current electrode of the first transistor of the second conductivity type;

a fourth transistor (204, 306, 404) of the first conductivity type having a control electrode coupled to the second current electrode of the first transistor of the second conductivity type, a first current electrode coupled to the second current electrode of the second transistor of the second conductivity type, and a second current electrode coupled to the fourth power supply terminal; and

an inverting circuit (216, 316, 416) coupled to the third and fourth power supply terminals having an input coupled to the second current electrode of the second transistor of the second conductivity type and an output coupled to the control electrode of the first transistor of the first conductivity type.

2. The circuit of claim 1, wherein the first, second, third, and fourth transistors of the first conductivity type have the same channel length and channel width.

3. The circuit of claim 2, wherein the first and second transistors of the second conductivity type have the same channel length and channel width.

4. The circuit of claim 1, wherein the circuit has a minimum channel length and minimum channel width for transistors and the first, second, third, and fourth transistors of the first conductivity type have the minimum channel length and channel width.

5. The circuit of claim 4, wherein the first and second transistors of the second conductivity type have the minimum channel length and channel width.

6. The circuit of claim 1, wherein the first conductivity type is N channel and the second conductivity type is P channel.

7. The circuit of claim 6, wherein the first and third power supply terminals are configured to receive a first voltage at a first level, the second power supply terminal is configured to receive a second voltage that is negative with respect to the first voltage, and the fourth power supply terminal is configured to receive a third voltage that is more negative than the second voltage with respect to the first voltage.

8. The circuit of claim 1, wherein the second conductivity type is N channel and the first conductivity type is P channel.

9. The circuit of claim 8, wherein the first and third power supply terminals are configured to receive a first voltage at a first level, the second power supply terminal is configured to receive a second voltage that is positive with respect to the first voltage, and the fourth power supply terminal is configured to receive a third voltage that is more positive than the second voltage with respect to the first voltage.

10. The circuit of claim 1, wherein the level translator further comprises;

a fifth transistor (416) of the first conductivity type, interposed between the control electrode of the second transistor of the second conductivity type and the second logic signal, having a first current electrode that receives the second logic signal (IN2), a control electrode coupled to the first power supply terminal (VDD1), and a second current electrode coupled to the control electrode of the second transistor of the second conductivity type;

a third transistor (422) of the second conductivity type, interposed between the control electrode of the second transistor of the second conductivity type and the second logic signal, having a first current electrode that receives the second logic signal, a control electrode coupled to the output of the inverting circuit, and a second current electrode coupled to the control electrode of the second transistor of the second conductivity type;

a fourth transistor (420) of the second conductivity type having a control electrode that receives the first logic signal; and

a fifth transistor (418) of the second conductivity type having a control electrode coupled to the second current electrode of the second transistor of the second conductivity type, wherein first and second current electrodes of the fourth and fifth transistors of the second conductivity type are coupled in series between the third power supply terminal and the second current electrode of the third transistor of the second conductivity type.

11. The circuit of claim 10, wherein:

the first, second, third, fourth, and fifth transistors of the first conductivity type and the first, second, third, fourth, and fifth transistors of the second conductivity type have the same channel length and channel width.

12. The circuit of claim 10, wherein:

the first, second, third, fourth, and fifth transistors of the first conductivity type and the first, second, third, fourth, and fifth transistors of the second conductivity type have the same channel length and channel width.

13. The circuit of claim 10, wherein the first conductivity type is N channel, the second conductivity type is P channel, the first power supply terminal is configured to receive a first voltage at a first level, the second power supply terminal is configured to receive a second voltage that is negative with respect to the first voltage, the third power supply terminal is configured to receive a third voltage that is positive relative to the first voltage, and the fourth power supply terminal is configured to receive a fourth voltage that is negative relative to the second voltage.

14. The circuit of claim 10, wherein the first conductivity type is P channel, the second conductivity type is N channel, the first power supply terminal is configured to receive a first voltage at a first level, the second power supply terminal is configured to receive a second voltage that is positive with respect to the first voltage, the third power supply terminal is configured to receive a third voltage that is negative relative to the first voltage, and the fourth power supply terminal is configured to receive a fourth voltage that is positive relative to the second voltage.

15. The circuit of claim 10, wherein the inverting circuit comprises:

a sixth transistor of the first conductivity type having a first current electrode coupled to the fourth power supply terminal, a control electrode coupled to the second current electrode of the fourth transistor of the first conductivity type, and a second current electrode coupled to the control electrode of the first transistor of the first conductivity type; and

a sixth transistor of the second conductivity type having a first current electrode coupled to the third power supply terminal, a control electrode coupled to the second current electrode of the fourth transistor of the first conductivity type, and a second current electrode coupled to the control electrode of the third transistor of the second conductivity type.

16. A circuit, comprising:

an output circuit (202, 302) in a first power supply domain configured to have a first voltage differential between a first power supply terminal and a second power supply terminal, wherein the output circuit receives a first logic signal (IN1) that switches between a first logic state based on a voltage at the first power supply terminal (VDD1) and a second logic state based on a voltage at the second power supply terminal (VSS1) and provides a second logic signal (IN2), complementary to the first logic signal, that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal; and

a level translator in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential, comprising;

a first transistor (214, 314) of a first type having a first current electrode for receiving the first logic signal, a second current electrode, and a control electrode;

a first transistor (208, 308) of a second type having a first current electrode for receiving the first logic signal, a second current electrode coupled to the second current electrode of the first transistor of the first type, and a control electrode coupled to the second power supply terminal;

a second transistor (206, 304) of the second conductivity type having a gate that receives the first input signal, a source coupled to a third power supply terminal (VDD2, VSS2), and a drain as a first output terminal of the level translator;

a second transistor (212, 312) of the first conductivity type having a drain coupled to the second current electrode of the first transistor of the second conductivity type, a gate configured to receive the first logic signal, and a source;

a third transistor (210, 310) of the first conductivity type having a drain coupled to the source of the second transistor of the first conductivity type, a source coupled to a fourth power supply terminal (VSS2, VDD2); and

a gate coupled to the first output terminal;

a fourth transistor (204, 306) of the first conductivity type having a gate coupled to the second current electrode of the first transistor of the second conductivity type, a drain coupled to the first output terminal, and a source coupled to the fourth power supply terminal; and

an inverting circuit (216, 316) coupled to the third and fourth power supply terminals having an input coupled to the first output terminal and an output coupled to the control electrode of the first transistor of the first conductivity type.

17. The circuit of claim 16, wherein the first, second, third, and fourth transistors of the first conductivity type have the same channel length and channel width.

18. The circuit of claim 16, wherein the circuit has a minimum channel length and minimum channel width for transistors and the first, second, third, and fourth transistors of the first conductivity type have the minimum channel length and channel width.

19. The circuit of claim 16, wherein the level translator further comprises;

a fifth transistor (416) of the first conductivity type having a first current electrode that receives the second logic signal, a control electrode coupled to the first power supply terminal, and a second current electrode coupled to the gate of the second transistor of the second conductivity type;

a third transistor (422) of the second conductivity type having a first current electrode that receives the second logic signal, a control electrode coupled to the output of the inverting circuit, and a second current electrode coupled to the gate of the second transistor of the second conductivity type;

a fourth transistor (420) of the second conductivity type having a drain coupled to the second current electrode of the third transistor of the second conductivity type, a gate configured to receive the second logic signal, and a source; and

a fifth transistor (418) of the second conductivity type having a drain coupled to the source of the fourth transistor of the second conductivity type, a source coupled to the third power supply terminal (VDD2); and

a gate coupled to the first output.

20. A circuit designed using transistors, wherein a subset of the transistors have the shortest channel length and narrowest channel width, comprising:

an output circuit (202, 302) in a first power supply domain configured to have a first voltage differential between a first power supply terminal and a second power supply terminal, wherein the output circuit receives a first logic signal (IN1) that switches between a first logic state based on a voltage at the first power supply terminal (VDD1) and a second logic state based on a voltage at the second power supply terminal (VSS1) and provides a second logic signal (IN2), complementary to the first logic signal, that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal; and

a level translator having in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential, comprising;

from the subset, a first transistor (214, 314) of a first type having a first current electrode for receiving the first logic signal, a second current electrode, and a control electrode;

from the subset, a first transistor (208, 308) of a second type having a first current electrode for receiving the first logic signal, a second current electrode coupled to the second current electrode of the first transistor of the first type, and a control electrode coupled to the second power supply terminal;

from the subset, a second transistor (206, 304) of the second conductivity type having a gate that receives the first input signal, a source coupled to a third power supply terminal (VDD2, VSS2), and a drain as a first output terminal of the level translator;

from the subset, a second transistor (212, 312) of the first conductivity type having a drain coupled to the second current electrode of the first transistor of the second conductivity type, a gate configured to receive the first logic signal, and a source;

from the subset, a third transistor (210, 310) of the first conductivity type having a drain coupled to the source of the second transistor of the first conductivity type, a source coupled to a fourth power supply terminal (VSS2, VDD2); and

a gate coupled to the first output terminal;

from the subset, a fourth transistor (204, 306) of the first conductivity type having a gate coupled to the second current electrode of the first transistor of the second conductivity type, a drain coupled to the first output terminal, and a source coupled to the fourth power supply terminal; and

an inverting circuit (216, 316) coupled to the third and fourth power supply terminals having an input coupled to the first output terminal and an output coupled to the control electrode of the first transistor of the first conductivity type, wherein the inverting circuit comprises transistors from the subset.