Clock recovery circuit

• US 9,209,966 B1
• Filed: 04/15/2015
• Issued: 12/08/2015
• Est. Priority Date: 12/07/2012
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Hossain, Masum, Zerbe, Jared L., Park, Myeong-Jae
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US14/687,766
• Time in Patent Office: 237 Days
• Field of Search: 375/355, 375/371, 375/373, 375/374, 375/376, 327/155, 327/156, 327/157
• US Class Current: 1/1
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 2025/03445 Time domain
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator'"'"'s (VFO'"'"'s) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

Claims

1. An integrated circuit, comprising:

a receiver to receive a digital signal from a signal path; and

a clock recovery circuit to generate a recovered clock from the digital signal;

wherein the clock recovery circuit

is to receive a first phase detection signal representing a comparison of timing of the digital signal with timing of the recovered clock signal, the first phase detection signal to vary linearly with phase difference,

is to receive a second phase detection signal representing a binary comparison of the digital signal with timing of the recovered clock signal, and

comprises a variable frequency oscillator to generate the recovered clock in dependence on each of the first phase detection signal and the second phase detection signal.

2. The integrated circuit of claim 1, wherein:

the variable frequency oscillator is to generate multiple phases of the recovered clock, the multiple phases respectively separated by constant phase offset;

the clock recovery circuit further comprises an accumulator to receive the second phase detection signal and accumulate a phase difference, a phase interpolator to receive the multiple phases and to generate an interpolated clock, the phase interpolator controlled in dependence on the accumulated phase difference, and a phase frequency detector to receive the interpolated clock and to compare the interpolated clock with a timing reference to generate an output; and

the variable frequency oscillator is further to generate the recovered clock in dependence on an output of the phase frequency detector.

3. The integrated circuit of claim 2, wherein said integrated circuit comprises a connection pin to receive the timing reference as an externally-supplied signal input to said integrated circuit.

4. The integrated circuit of claim 2, wherein the clock recovery circuit further comprises a low pass filter to filter the output of the phase frequency detector, and a charge pump to receive an output of the low pass filter and to responsively generate a control signal having a variable magnitude, the variable frequency oscillator to generate the recovered clock to have a frequency that varies according to the magnitude of the control signal.

5. The integrated circuit of claim 1, wherein the clock recovery circuitry comprises hybrid phase detector circuitry having circuit elements that are to generate both of the first phase detection signal and the second phase detection signal.

6. The integrated circuit of claim 1, wherein the clock recovery circuit comprises linear phase detection circuitry that is to generate the first phase detection signal and binary phase detection circuitry that is to generate the second phase detection signal.

7. The integrated circuit of claim 1, wherein the variable frequency oscillator is to receive a control signal dependent on a sum of (1) an integrated version of the second phase detection signal, and (2) the first phase detection signal, and is to generate the recovered clock independence on the control signal.

8. The integrated circuit of claim 1, wherein:

the clock recovery circuit comprises two feedback loops, including

a first feedback loop dependent on the first phase detection signal, and

a second feedback loop dependent on the second phase detection signal;

the first feedback loop is to respond to changes in timing of the digital signal with a greater loop bandwidth than the second feedback loop.

9. The integrated circuit of claim 8, wherein:

the second feedback loop comprises a second order correction circuit to generate an output that varies according to both of the second phase detection signal and an integral of the second phase detection signal.

10. The integrated circuit of claim 8, wherein the digital signal is adapted to carry timing for a spread spectrum clock signal and wherein:

the second feedback loop comprises a third order correction circuit to generate an output that varies according to all of the second phase detection signal, the integral of the second phase detection signal, and the integral of the integral of the second phase detection signal.

11. The integrated circuit of claim 1, further comprising a continuous time linear equalizer (CTLE), the CTLE to receive an input signal and to equalize the input signal according to frequency of data values carried by the input signal, to generate the digital signal as an equalized version of the input signal.

12. The integrated circuit of claim 1, further comprising a deserializer to receive sampled data values from the receiver, the deserializer controlled dependent on the recovered clock to generate a parallel data word from time-separated symbols carried by the digital signal.

13. The integrated circuit of claim 1, further comprising circuitry to detect a predetermined bit pattern carried by the digital signal, and to restrict updates in the recovered clock responsive to the second phase detection signal to occur responsive to detection of the predetermined bit pattern.

14. An integrated circuit to receive digital signals from respective, external signaling lanes, the integrated circuit comprising:

for each signaling lane, a receiver to receive the respective digital signal; and

a clock recovery circuit to generate a recovered clock from at least one of the digital signals;

wherein the clock recovery circuit

is to receive a first input to receive a first phase detection signal representing a comparison of timing of the at least one of the digital signals with timing of the recovered clock signal, the first phase detection signal to vary linearly with phase difference,

is to receive a second phase detection signal representing a binary comparison of the at least one of the digital signals with timing of the recovered clock signal, and

comprises a variable frequency oscillator to generate the recovered clock in dependence on each of the first phase detection signal and the second phase detection signal.

15. The integrated circuit of claim 14, wherein:

the clock recovery circuit is a first clock recovery circuit; and

the integrated circuit comprises clock recovery circuits that are respective to the signaling lanes, the clock recovery circuits including the first clock recovery circuit, each of the clock recovery circuits

to receive a first phase detection signal representing a comparison of timing the respective digital signal with timing of a respective recovered clock signal, the first phase detection signal to vary linearly with phase difference,

to receive a second phase detection signal representing a binary comparison of the respective digital signal with timing of the respective recovered clock signal, and

comprises a variable frequency oscillator to generate the respective recovered clock in dependence on each of the respective first phase detection signal and the respective second phase detection signal.

16. The integrated circuit of claim 15, wherein the integrated circuit has a first mode, in which each of the clock recovery circuits are to independently generate the respective recovered clock in dependence on the respective digital signal, and a second mode, in which one of the clock recovery circuits is to act as a master, and each other of the clock recovery circuits is to act as a slave to timing updates generated by the master.

17. The integrated circuit of claim 14, wherein:

the variable frequency oscillator is to generate multiple phases of the recovered clock, the multiple phases respectively separated by constant phase offset;

the clock recovery circuit further comprises an accumulator to receive the second phase detection signal and accumulate a phase difference, a phase interpolator to receive the multiple phases and to generate an interpolated clock, the phase interpolator controlled in dependence on the phase difference, and a phase frequency detector to receive the interpolated clock and to compare the interpolated clock with a timing reference; and

the variable frequency oscillator is further to generate the recovered clock in dependence on an output of the phase frequency detector.

18. The integrated circuit of claim 17, wherein said integrated circuit comprises a connection pin to receive the timing reference as an externally-supplied signal input to said integrated circuit.

19. The integrated circuit of claim 14, wherein the clock recovery circuit further comprises a low pass filter to filter the output of the phase frequency detector, and a charge pump to receive an output of the low pass filter and to generate a control signal having a variable magnitude, the variable frequency oscillator to generate the recovered clock to have a frequency that varies according to the magnitude of the control signal.

20. The integrated circuit of claim 14, wherein the variable frequency oscillator is to receive a control signal dependent on a sum of (1) an integrated version of the second phase detection signal, and (2) the first phase detection signal, and is to generate the recovered clock independence on the control signal.

21. The integrated circuit of claim 14, wherein:

the clock recovery circuit comprises two feedback loops, including

a first feedback loop dependent on the first phase detection signal, and

a second feedback loop dependent on the second phase detection signal;

the first feedback loop is to respond to changes in timing of the at least one of the digital signals with a greater loop bandwidth than the second feedback loop.

22. The integrated circuit of claim 14, further comprising for each signaling lane a continuous time linear equalizer (CTLE), each CTLE to receive an input signal from the respective signaling lane and to equalize the respective input signal according to frequency of data values carried by the respective input signal, to generate the respective digital signal as an equalized version of the respective input signal.

23. The integrated circuit of claim 14, further comprising for each signaling lane:

a deserializer to receive sampled data values from the respective receiver, the deserializer to be controlled dependent on the recovered clock to generate a parallel data word from time-separated symbols carried by the respective digital signal.