Adaptive data re-compaction after post-write read verification operations
First Claim
1. A method of operating a non-volatile memory system including one or more non-volatile memory circuits each having one or more arrays of non-volatile memory cells formed along word lines as a plurality of erase blocks, each erase block corresponding to a plurality of word lines, the method comprising:
- storing a first plurality of pages of data in a first section of the non-volatile memory system;
subsequently programing the first plurality of pages from the first section into a first plurality of word lines of a first block of the memory system, wherein the first plurality of word lines is less than all of the word lines of the first block;
determining whether the first plurality of data pages were programmed correctly into the first plurality of word lines;
generating one or more pages of parity data from the first plurality of data pages, where the parity data is generated only from those of the first plurality of data pages that were determined to be programmed correctly into the first plurality of word lines; and
writing the generated pages of parity data into one or more second word lines of the first block other than those of the first plurality of word lines.
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Accused Products
Abstract
Approaches are presented for adaptively re-compacting data when errors are found during a post-write verify in a non-volatile memory system, such as flash NAND memory. In one example, user data along with corresponding parity data is written into a block of non-volatile memory. After writing in the user data, but prior to writing the corresponding parity data, the user data is checked. For any word lines that fail this post-write verify, the parity data for the block is adjusted to remove the contribution of any failed word lines before this modified parity data is written into the block. The data corresponding to the failed word lines can then be written elsewhere in the memory system.
61 Citations
19 Claims
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1. A method of operating a non-volatile memory system including one or more non-volatile memory circuits each having one or more arrays of non-volatile memory cells formed along word lines as a plurality of erase blocks, each erase block corresponding to a plurality of word lines, the method comprising:
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storing a first plurality of pages of data in a first section of the non-volatile memory system; subsequently programing the first plurality of pages from the first section into a first plurality of word lines of a first block of the memory system, wherein the first plurality of word lines is less than all of the word lines of the first block; determining whether the first plurality of data pages were programmed correctly into the first plurality of word lines; generating one or more pages of parity data from the first plurality of data pages, where the parity data is generated only from those of the first plurality of data pages that were determined to be programmed correctly into the first plurality of word lines; and writing the generated pages of parity data into one or more second word lines of the first block other than those of the first plurality of word lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19)
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16. The method of clam 1, wherein generating the pages of parity data includes modifying previously generated pages of parity data to exclude the contribution thereto of data pages that were determined to not be programmed correctly.
Specification