Data processing method, and memory controller and memory storage device using the same

• US 9,213,631 B2
• Filed: 07/23/2012
• Issued: 12/15/2015
• Est. Priority Date: 05/11/2012
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Chu, Chien-Hua
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US13/555,206
• Publication Number:
  US 20130304964A1
• Time in Patent Office: 1,240 Days
• Field of Search: 711/103, 707/755
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A data processing method for a re-writable non-volatile memory module is provided. The method includes receiving a write data stream associating to a logical access address of a logical programming unit; selecting a physical programming unit; and determining whether the write data stream associates with a kind of pattern. The method includes, if the write data stream associates with the kind of pattern, setting identification information corresponding to the logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the logical access address into a predetermined area, wherein the write data stream is not programmed into the selected physical programming unit. The method further includes mapping the logical programming unit to the physical programming unit. Accordingly, the method can effectively shorten the time for writing data into the re-writable non-volatile memory module.

Claims

1. A data processing method for a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, a plurality of logical programming units is configured to map to at least a portion of the plurality of physical programming units, and each of the plurality of logical programming units has a plurality of logical access addresses, the data processing method comprising:

receiving a first write data stream, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units;

selecting a first physical programming unit from the plurality of physical programming units;

determining whether the first write data stream associates with a pattern;

if the first write data stream does not associate with the pattern, setting identification information corresponding to the first logical access address as a default value, programming the first write data stream into the first logical access address among the plurality of logical access addresses in the data bit area of the first physical programming unit and storing the identification information corresponding to the first logical access address in a predetermined area;

if the first write data stream associates with the pattern, setting the identification information corresponding to the first logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the first logical access address in the predetermined area, wherein the first write data stream is not programmed into the first physical programming unit; and

mapping the first logical programming unit to the first physical programming unit,

wherein a step of storing the identification information corresponding to the first logical access address to the predetermined area comprises;

programming the identification information corresponding to the first logical access address into the redundancy bit area of the first physical access address.

2. The data processing method as recited in claim 1, further comprising:

receiving a read command from a host system, wherein the read command instructs to read data stored in the first logical access address;

reading a read data stream associating to the first logical access address and the identification information corresponding to the first logical access address from the first physical programming unit;

determining whether the identification information corresponding to the first logical access address read from the first physical programming unit is the identification value;

if the identification information corresponding to the first logical access address read from the first physical programming unit is the identification value, transmitting a predetermined data corresponding to the pattern to the host system; and

if the identification information corresponding to the first logical access address read from the first physical programming unit is not the identification value, transmitting the read data stream to the host system.

3. The data processing method as recited in claim 1, further comprising:

determining whether a valid data stream associating to a second logical access address among the plurality of logical access addresses of the first logical programming unit is stored in the re-writable non-volatile memory module;

if the valid data stream associating to the second logical access address is stored in the re-writable non-volatile memory module, setting the identification information corresponding to the second logical access address as the default value, programming the valid data stream into a second physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit, and programming the identification information corresponding to the second logical access address into the redundancy bit area of the first physical access address; and

if the valid data stream associating to the second logical access address is not stored in the re-writable non-volatile memory module, setting the identification corresponding to the second logical access address as the identification value and programming the identification information corresponding to the second logical access address into the redundancy bit area of the first physical access address.

4. The data processing method as recited in claim 1, further comprising:

receiving a second write data stream, wherein the second write data stream associates with a second logical access address among the plurality of logical access addresses of the first logical programming unit;

determining whether the second write data stream associates with the pattern;

if the second write data stream does not associate with the pattern, setting the identification information corresponding to the second logical access address as the default value, programming the second write data stream into the second logical access address among the plurality of logical access addresses in the data bit area of the first physical programming unit and programming the identification information corresponding to the second logical access address into the redundancy bit area of the first physical programming unit; and

if the second write data stream associates with the pattern, setting the identification information corresponding to the second logical access address as the identification value corresponding to the pattern and programming the identification information corresponding to the second logical access address into the redundancy bit area of the first physical programming unit, wherein the second write data stream is not programmed into the first physical programming unit.

5. The data processing method as recited in claim 4, wherein the first write data stream, the second write data stream, the identification information corresponding to the first logical access address, the identification information corresponding to the second logical access address are programmed into the first physical programming unit by a programming command.

6. The data processing method as recited in claim 1, wherein a step of determining whether the first write data stream associates with the pattern comprises:

determining whether each data bit of the first write data stream is 0; and

if each data bit of the first write data stream is 0, identifying that the first write data stream associates with the pattern.

7. A data processing method for a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, a plurality of logical programming units is configured to map to a portion of the plurality of physical programming units, and each of the plurality of logical programming units has a plurality of logical access addresses, the data processing method comprising:

receiving a first write data stream, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units;

selecting a first physical programming unit from the plurality of physical programming units;

determining whether the first write data stream associates with one of a plurality of patterns;

if the first write data stream does not associate with any one of the plurality of patterns, setting identification information corresponding to the first logical access address as a default value, programming the first write data stream into a first physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit and programming the identification information corresponding to the first logical access address into the redundancy bit area of the first physical programming unit;

if the first write data stream associates with one of the plurality of patterns, setting the identification information corresponding to the first logical access address as an identification value and programming the identification information corresponding to the first logical access address into the redundancy bit area of the first physical programming unit, wherein the first write data stream is not programmed into the first physical programming unit; and

mapping the first logical programming unit to the first physical programming unit.

8. The data processing method as recited in claim 7, further comprising:

receiving a read command from a host system, wherein the read command instructs to read data stored in the first logical access address;

reading a read data stream associating to the first logical access address and the identification information corresponding to the first logical access address from the first physical programming unit;

determining whether the identification information corresponding to the first logical access address read from the first physical programming unit is the identification value corresponding to the one of the plurality of patterns;

if the identification information corresponding to the first logical access address read from the first physical programming unit is the identification value corresponding to the one of the plurality of patterns, transmitting a predetermined data corresponding to the one of the plurality of patterns to the host system; and

if the identification information corresponding to the first logical access address read from the first physical programming unit is not the identification value corresponding to the one of the plurality of patterns, transmitting the read data stream to the host system.

9. A memory controller for controlling a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, the memory controller comprising:

a host interface, configured to be coupled to a host system;

a memory interface, configured to be coupled to a rewritable non-volatile memory module; and

a memory management circuit, coupled to the host interface and the rewritable non-volatile memory module and configured to configure a plurality of logical programming units to map to at least a portion of the plurality of physical programming units, wherein each of the plurality of logical programming units has a plurality of logical access addresses,

wherein the memory management circuit is further configured to receive a first write data stream from the host system, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units,

wherein the memory management circuit is further configured to select a first physical programming unit from the plurality of physical programming units and determine whether the first write data stream associates with a pattern,

wherein if the first write data stream does not associate with the pattern, the memory management circuit is further configured to set identification information corresponding to the first logical access address as a default value, program the first write data stream into a first physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit and store the identification information corresponding to the first logical access address in a predetermined area,

wherein if the first write data stream associates with the pattern, the memory management circuit is further configured to set the identification information corresponding to the first logical access address as an identification value corresponding to the pattern and store the identification information corresponding to the first logical access address in the predetermined area, wherein the first write data stream is not programmed into the first physical programming unit, and

wherein the memory management circuit is further configured to map the first logical programming unit to the first physical programming unit,

wherein the predetermined area is the redundancy bit area of the first physical programming unit.

10. The memory controller as recited in claim 9, wherein the memory management circuit is further configured to receive a read command from a host system, wherein the read command instructs to read data stored in the first logical access address,

wherein the memory management circuit is further configured to read a read data stream associating to the first logical access address and the identification information corresponding to the first logical access address from the first physical programming unit and determine whether the identification information corresponding to the first logical access address read from the first physical programming unit is the identification value,

wherein if the identification information corresponding to the first logical access address read from the first physical programming unit is the identification value, the memory management circuit is further configured to transmit a predetermined data corresponding to the pattern to the host system, and

wherein if the identification information corresponding to the first logical access address read from the first physical programming unit is not the identification value, the memory management circuit is further configured to transmit the read data stream to the host system.

11. The memory controller as recited in claim 9, wherein the memory management circuit is further configured to determine whether a valid data stream associating to a second logical access address among the plurality of logical access addresses of the first logical programming unit is stored in the re-writable non-volatile memory module,

wherein if the valid data stream associating to the second logical access address is stored in the re-writable non-volatile memory module, the memory management circuit is further configured to set the identification information corresponding to the second logical access address as the default value, program the valid data stream into a second physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit, and program the identification information corresponding to the second logical access address into the redundancy bit area of the first physical access address, and

where if the valid data stream associating to the second logical access address is not stored in the re-writable non-volatile memory module, the memory management circuit is further configured to set the identification information corresponding to the second logical access address as the identification value corresponding to the pattern and program the identification information corresponding to the second logical access address into the redundancy bit area of the first physical access address.

12. The memory controller as recited in claim 9, wherein the memory management circuit is further configured to receive a second write data stream from the host system via the host interface, wherein the second write data stream associates with a second logical access address among the plurality of logical access addresses of the first logical programming unit,

wherein the memory management circuit is further configured to determine whether the second write data stream associates with the pattern,

wherein if the second write data stream does not associate with the pattern, the memory management circuit is further configured to set the identification information corresponding to the second logical access address as the default value, program the second write data stream into the second logical access address among the plurality of logical access addresses in the data bit area of the first physical programming unit and program the identification information corresponding to the second logical access address into the redundancy bit area of the first physical programming unit, and

where if the second write data stream associates with the pattern, the memory management circuit is further configured to set the identification information corresponding to the second logical access address as the identification value corresponding to the pattern and program the identification information corresponding to the second logical access address into the redundancy bit area of the first physical programming unit, wherein the second write data stream is not programmed into the first physical programming unit.

13. The memory controller as recited in claim 12, wherein the memory management circuit is further configured to program the first write data stream, the second write data stream, the identification information corresponding to the first logical access address, the identification information corresponding to the second logical access address into the first physical programming unit by using a programming command.

14. The memory controller as recited in claim 9, wherein the memory management circuit is further configured to determine whether each data bit of the first write data stream is 0, and

where if each data bit of the first write data stream is 0, the memory management circuit identifies that the first write data stream associates with the pattern.

15. A memory storage device, comprising:

a connector, configured to be coupled to a host system;

a rewritable non-volatile memory module, having a plurality of physical programmed blocks, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, and the data bit area has a plurality of physical access addresses; and

a memory controller, coupled to the connector and the rewritable non-volatile memory module and configured to configure a plurality of logical programming units to be mapped to at least a portion of the plurality of physical programming units, wherein each of the plurality of logical programming units has a plurality of logical access addresses,

wherein the memory controller is further configured to receive a first write data stream from the host system, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units,

wherein the memory controller is further configured to select a first physical programming unit from the plurality of physical programming units and determine whether the first write data stream associates with a pattern,

wherein if the first write data stream does not associate with the pattern, the memory controller is further configured to set identification information corresponding to the first logical access address as a default value, program the first write data stream into a first physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit and store the identification information corresponding to the first logical access address in a predetermined area,

wherein if the first write data stream associates with the pattern, the memory controller is further configured to set the identification information corresponding to the first logical access address as an identification value corresponding to the pattern and store the identification information corresponding to the first logical access address in the predetermined area, wherein the first write data stream is not programmed into the first physical programming unit, and

wherein the memory controller is further configured to map the first logical programming unit to the first physical programming unit,

wherein the predetermined area is the redundancy bit area of the first physical programming unit.

16. The memory storage device as recited in claim 15, wherein the memory controller is further configured to receive a read command from a host system, wherein the read command instructs to read data stored in the first logical access address,

wherein the memory controller is further configured to read a read data stream associating to the first logical access address and the identification information corresponding to the first logical access address from the first physical programming unit and determine whether the identification information corresponding to the first logical access address read from the first physical programming unit is the identification value,

wherein if the identification information corresponding to the first logical access address read from the first physical programming unit is the identification value, the memory controller is further configured to transmit a predetermined data corresponding to the pattern to the host system, and

wherein if the identification information corresponding to the first logical access address read from the first physical programming unit is not the identification value, the memory management circuit is further configured to transmit the read data stream to the host system.

17. The memory storage device as recited in claim 15, wherein the memory controller is further configured to determine whether a valid data stream associating to a second logical access address among the plurality of logical access addresses of the first logical programming unit is stored in the re-writable non-volatile memory module,

wherein if the valid data stream associating to the second logical access address is stored in the re-writable non-volatile memory module, the memory controller is further configured to set the identification information corresponding to the second logical access address as the default value, program the valid data stream into a second physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit, and program the identification information corresponding to the second logical access address into the redundancy bit area of the first physical access address, and

where if the valid data stream associating to the second logical access address is not stored in the re-writable non-volatile memory module, the memory controller is further configured to set the identification information corresponding to the second logical access address as the identification value corresponding to the pattern and program the identification information corresponding into the second logical access address to the redundancy bit area of the first physical access address.

18. The memory storage device as recited in claim 15, wherein the memory controller is further configured to receive a second write data stream from the host system via the host interface, wherein the second write data stream associates with a second logical access address among the plurality of logical access addresses of the first logical programming unit,

wherein the memory controller is further configured to determine whether the second write data stream associates with the pattern,

wherein if the second write data stream does not associate with the pattern, the memory controller is further configured to set the identification information corresponding to the second logical access address as the default value, program the second write data stream into the second logical access address among the plurality of logical access addresses in the data bit area of the first physical programming unit and program the identification information corresponding to the second logical access address into the redundancy bit area of the first physical programming unit, and

where if the second write data stream associates with the pattern, the memory management circuit is further configured to set the identification information corresponding to the second logical access address as the identification value corresponding to the pattern and program the identification information corresponding to the second logical access address into the redundancy bit area of the first physical programming unit, wherein the second write data stream is not programmed into the first physical programming unit.

19. The memory storage device as recited in claim 18, wherein the memory controller is further configured to program the first write data stream, the second write data stream, the identification information corresponding to the first logical access address, the identification information corresponding to the second logical access address into the first physical programming unit by using a programming command.

20. The memory storage device as recited in claim 15, wherein the memory controller is further configured to determine whether each data bit of the first write data stream is 0, and

where if each data bit of the first write data stream is 0, the memory management circuit identifies that the first write data stream associates with the pattern.

21. A memory storage device, comprising:

a connector, configured to be coupled to a host system;

a rewritable non-volatile memory module, having a plurality of physical programmed blocks, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, and the data bit area has a plurality of physical access addresses; and

a memory controller, coupled to the connector and the rewritable non-volatile memory module and is configured to configure a plurality of logical programming units to be mapped to a portion of the plurality of physical programming units, wherein each of the plurality of logical programming units has a plurality of logical access addresses,

wherein the memory controller is further configured to receive a first write data stream from the host system, wherein the first write data stream associates with a first logical access address among the plurality of logical access addresses, and the first logical access address associates with a first logical programming unit among the plurality of logical programming units,

wherein the memory controller is further configured to select a first physical programming unit from the plurality of physical programming units and determine whether the first write data stream associates with a pattern among multiple patterns,

wherein if the first write data stream does not associate with any one of the multiple patterns, the memory controller is further configured to set identification information corresponding to the first logical access address as a default value, program the first write data stream into a first physical access address among the plurality of physical access addresses in the data bit area of the first physical programming unit and program the identification information corresponding to the first logical access address into the redundancy bit area of the first physical programming unit;

wherein if the first write data stream associates with one of the multiple patterns, the memory controller is further configured to set the identification information corresponding to the first logical access address as an identification value corresponding to the pattern and program the identification information corresponding to the first logical access address into the redundancy bit area of the first physical programming unit, wherein the first write data stream is not programmed into the first physical programming unit; and

wherein the memory controller is further configured to map the first logical programming unit to the first physical programming unit.

22. The memory storage device as recited in claim 21, wherein the memory controller is further configured to receive a read command from the host system, wherein the read command instructs to read data stored in the first logical access address,

wherein the memory controller is further configured to read a read data stream associating to the first logical access address and the identification information corresponding to the first logical access address from the first physical programming unit and determine whether the identification info nation corresponding to the first logical access address read from the first physical programming unit is the identification value corresponding to the one of the patterns,

wherein if the identification information corresponding to the first logical access address read from the first physical programming unit is the identification value corresponding to the one of the patterns, the memory controller is further configured to transmit a predetermined data corresponding to the one of the patterns to the host system, and

wherein if the identification information corresponding to the first logical access address read from the first physical programming unit is not the identification value corresponding to the one of the patterns, the memory controller is further configured to transmit the read data stream to the host system.

23. A data processing method for a re-writable non-volatile memory module having a plurality of physical programming units, wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area has a plurality of physical access addresses, a plurality of logical programming units is configured to be mapped to at least a portion of the plurality of physical programming units, and each of the plurality of logical programming units has a plurality of logical access addresses, the data processing method comprising,

receiving a read command from a host system, wherein the read command instructs to read data stored in a first logical access address among the plurality of logical access addresses;

reading identification information corresponding to the first logical access address from a predetermined area;

determining whether the identification information is an identification value;

transmitting a predetermined data to the host system if the read identification information is the identification value; and

transmitting a data stream read from a physical access address mapped to the first logical access address to the host system if the identification information is not the identification value,

wherein the number of bits of the identification value is smaller than the number of bits of the predetermined data,

wherein the predetermined area is the redundancy bit area of the first physical programming unit.