Managing cache access and streaming data

• US 9,213,652 B1
• Filed: 09/20/2010
• Issued: 12/15/2015
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Tilera Corperation
• Inventors: Miao, Chyi-Chang, Metcalf, Christopher D., Bratt, Ian Rudolf, Ramey, Carl G.
• Primary Examiner(s): Farrokh, Hashem
• Application Number:
  US12/886,365
• Time in Patent Office: 1,912 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1482 by means of middleware or OS functionality
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0844 Multiple simultaneous or quasi-simultaneous cache accessing
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4221 : being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 15/16 : Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 15/8023 : Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 21/79 : in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/452 : Instruction code
• CPC Class Codes: G06F 2212/502 : using adaptive policy
• CPC Class Codes: G06F 2212/601 : Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/6032 : Way prediction in set-associative cache
• CPC Class Codes: G06F 2212/621 : Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 9/3004 : to perform operations on memory
• CPC Class Codes: G06F 9/4825 : Interrupt from clock, e.g. time of day
• CPC Class Codes: G06F 9/4881 : Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/5022 : Mechanisms to release resources
• CPC Class Codes: G06F 9/544 : Buffers; Shared memory; Pipes
• CPC Class Codes: H04L 45/08 : Learning-based routing, e.g. using neural networks or artificial intelligence
• CPC Class Codes: H04L 45/22 : Alternate routing
• CPC Class Codes: H04L 45/28 : using route fault recovery
• CPC Class Codes: H04L 47/823 : Prediction of resource usage
• CPC Class Codes: H04L 47/83 : based on usage prediction
• CPC Class Codes: H04L 49/109 : Integrated on microchip, e.g. switch-on-chip

Abstract

Managing data in a computing system comprising one or more cores includes: providing a cache in each of one or more of the cores that includes multiple storage locations; storing data of a first type of multiple types of data in a selected storage location of a first cache of a first core that is selected according to status information associated with the first cache, and updating the status information; and storing data of a second type of the multiple types of data in a storage location within a subset of fewer than all of the storage locations of the first cache and managing the status information to ensure that subsequent data of the second type received by the first core for storage in the first cache is stored in the storage location within the subset.

Claims

1. A method for managing data in a computing system comprising one or more cores, the method comprising:

storing data of a first type of multiple types of data in one or more selected storage locations of a first cache of a first core, with the one or more selected storage locations being selected from multiple storage locations of the first cache according to least recently used status information associated with the first cache;

updating the least recently used status information after the data of the first type is stored;

receiving a request to store data of a second, different type of the multiple types;

setting a configuration indicator to not update the status information for the cache for data of the second, different type of the multiple types;

storing data of the second type of the multiple types of data in a second storage location of the first cache, where the second storage location does not include any of the one or more selected storage locations; and

managing the least recently used status information associated with the first cache to not update the status information of the second location for subsequent data of the second type received by the first core for storage in the first cache, and storing the data of the second type only in the second storage location.

2. The method of claim 1, wherein setting the configuration indicator, sets an indicator in a configuration register in response to execution of a software instruction for receiving the data of the second type.

3. The method of claim 2, wherein data of the first type received is stored in one or more of the selected storage locations according to a least recently used one of storage locations in the cache and for the data of the second type received, while the configuration information is set, the data of the second type will repeatedly overwrite data of the second type to store the second type data only the second storage location.

4. The method of claim 1, wherein the first type of multiple types of data comprises data that is written or read by an instruction issued by a processor of at least one of the cores.

5. The method of claim 1, wherein the second type of multiple types of data comprises data that is received by at least one of the cores from an input/output device coupled to at least one of the cores.

6. The method of claim 5, wherein the second type of multiple types of data comprises data that is streamed from the input/output device, and the first type of data comprises local data that is data local to processes running on the at least one of the cores.

7. The method of claim 1, wherein the first cache is a set-associative cache having multiple sets to which different addresses are mapped and each set having multiple ways, and the one or more storage locations includes a respective way in each set of the set-associative cache, and the least recently used status indicates which of the multiple ways in a given set stores data has been least recently used by a processor of at least one of the cores, and the selected storage location storing the data of the first type corresponds to the least recently used way of a set to which an address of the first type of data is mapped.

8. The method of claim 7, wherein setting the configuration indicator includes setting the indicator by writing to a register in the first core to cause the LRU status for a given set that corresponds to the second location to not be updated after storing data in the given set.

9. The method of claim 1, wherein the subsets of storage locations are respective ways of a set associative caching scheme.

10. A computing system, comprising:

a plurality of cores, each core comprising;

a cache that includes multiple storage locations; and

a processor;

with a processor in a first core configured to;

store data of a first type of multiple types of data in a selected, first storage location of a first cache of the first core, with the first storage location selected from multiple storage locations of the first cache according to least recently used status information associated with the first cache;

update the least recently used status information after the data of the first type is stored;

receive a request to store data of a second, different type of the multiple types;

set a configuration indicator to not update the status information for the cache for data of the second, different type of the multiple types;

store data of the second type of the multiple types of data in a second storage location of the first cache, where the second storage location does not include any of the one or more selected storage locations; and

manage the least recently used status information associated with the first cache to not update the status information of the second location for subsequent data of the second type received by the first core for storage in the first cache, and storing the data of the second type is stored only in the second storage location.

11. The computing system of claim 10, wherein the processor further configured to set a configuration indicator sets an indicator that is in a configuration register in response to execution of a software instruction for receiving the data of the second type.

12. The computing system of claim 10, wherein data of the first type received is stored in one or more of the selected storage locations according to a least recently used one of storage locations in the cache and for the data of the second type received, while the configuration information is set, the data of the second type will repeatedly overwrite data of the second type to store the second type data only the second storage location.

13. The computing system of claim 10, wherein the first type of multiple types of data comprises data that is written or read by an instruction issued by a processor of at least one of the cores.

14. The computing system of claim 10, wherein the second type of multiple types of data comprises data that is received by at least one of the cores from an input/output device coupled to at least one of the cores, and the first type of data comprises local data that is data local to processes running on the at least one of the cores.

15. The computing system of claim 14, wherein the second type of multiple types of data comprises data that is streamed from the input/output device.

16. The computing system of claim 10, wherein the processor configures the first cache that is a set-associative cache having multiple sets to which different addresses are mapped and each set having multiple ways, and the one or more storage locations includes a respective way in each set of the set-associative cache, and the least recently used status indicates which of the multiple ways in a given set stores data has been least recently used by a processor of at least one of the cores, and the selected storage location storing the data of the first type corresponds to the least recently used way of a set to which an address of the first type of data is mapped.

17. The computing system of claim 16, wherein the processor further configured to set the configuration indicator includes the processor configured to set the indicator by writing to a register in the first core to cause the LRU status for a given set that corresponds to the second location to not be updated after storing data in the given set.

18. The computing system of claim 10, wherein the subsets of storage locations are respective ways of a set associative caching scheme.