Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks

• US 9,213,793 B1
• Filed: 10/02/2013
• Issued: 12/15/2015
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Salowe, Jeffrey S.
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US14/044,836
• Time in Patent Office: 804 Days
• Field of Search: 716/126, 716/129, 716/130, 716/131
• US Class Current: 1/1
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

One aspect interconnects two regions subject to different rules and using transition rule(s) in a transition region or cost mechanism(s), where these rules may include soft rule(s), hard rule(s), or combinations thereof. These two regions may reside on the same routing layer or on different routing layers. This aspect allows physical design tools to transition across gridded, gridless, tracked, or trackless regions subject to different rules on the same or different layers. Another aspect interconnects an object subject to the first rule(s) and the second rule(s), while the object satisfies or violates the first rule(s). These aspects use spacetile(s) on a spacetile layer as search probe(s) to find viable implementation solutions, although the spacetile(s) and hence the search probe may violate one or more rules. A spacetile layer may be identified or created for each rule and may be associated with relevant features subject to relevant rule(s).

Claims

1. A computer implemented method for implementing electronic design using flexible routing tracks, comprising:

identifying, with a track pattern manipulation mechanism including or functioning in conjunction with at least one processor or at least one processor core of a computing system, a track pattern having multiple tracks and associated with a first routing rule for implementing at least a part of a net including a shape in a first region on a first layer, wherein the shape is associated with a first rule;

identifying or creating one or more spacetiles based at least in part upon the shape; and

implementing the at least a part of the net including the shape by using at least one spacetile of the one or more spacetiles as a search probe for implementation of the at least part of the net, wherein the at least one spacetile overlaps in part or in whole with at least the shape.

2. The computer implemented method of claim 1, the process further comprising:

identifying the net including the shape and the first rule; and

identifying the first routing rule associated with the multiple tracks.

3. The computer implemented method of claim 1, the process further comprising:

determining whether or not wrong-way tracks are to be used in implementing the at least a part of the net including the shape; and

identifying a spacetile as an area-based search probe from the one or more spacetiles, wherein the act of implementing the at least a part of the net is performed by further using the area-based search probe.

4. The computer implemented method of claim 3, the process further comprising:

identifying or creating a via spacetile layer for the first layer and a second layer immediately neighboring the first layer, wherein

the wrong-way tracks are disallowed in implementing the at least a part of the net including the shape; and

identifying the one or more spacetiles for the via spacetile layer by using at least one or more geometric components of the shape.

5. The computer implemented method of claim 4, the act of identifying the one or more spacetiles for the via spacetile layer comprising:

performing a spacetile punch process for the at least one or more geometric components of the shape to create a first set of spacetiles;

identifying a second set of zero or more spacetiles from the second layer;

aggregating the first set of spacetiles and the second set of zero or more spacetiles to form the one or more spacetiles; and

incorporating the one or more spacetiles into the via spacetile layer at corresponding locations.

6. The computer implemented method of claim 4, wherein the one or more geometric components include at least one of a centerline of the shape in a first direction and a boundary segment of the shape in the first direction.

7. The computer implemented method of claim 1, the process further comprising:

identifying multiple routing rules for implementing the at least a part of the net;

identifying one or more corresponding tracks for each routing rule of the multiple routing rules;

associating a respective spacetile layer with the each routing rule of the multiple routing rules; and

associating the respective spacetile layer with the one or more corresponding tracks identified for the each routing rule.

8. The computer implemented method of claim 1, the process further comprising:

determining a relation between the shape or a geometric component of the shape and at least one track of the multiple tracks.

9. The computer implemented method of claim 8, wherein the relation indicates whether or not the shape or the geometric component of the shape is aligned with the at least one track of the multiple tracks.

10. The computer implemented method of claim 8, the process further comprising:

determining whether wrong-way tracks are to be used to implement the at least a part of the net;

identifying a spacetile as a search probe from the one or more spacetiles; and

performing an area-based search for implementation solutions by using at least the search probe, wherein the act of implementing the at least a part of the net is performed by further using at least some of the implementation solutions.

11. The computer implemented method of claim 10, the process further comprising:

identifying a first spacetile layer for at least the first layer;

identifying a second spacetile layer for a second layer;

identifying or creating a via spacetile layer for the first layer and a second layer immediately neighboring the first layer, wherein no wrong-way tracks are permitted in implementing the at least a part of the net; and

aggregate the one or more spacetiles into the via spacetile layer from both the first spacetile layer and the second spacetile layer.

12. The computer implemented method of claim 8, the process further comprising:

determining whether or not a taper rule is allowed in implementing the at least a part of the net;

determining whether wrong-way tracks are to be used to implement the at least a part of the net; and

identifying or determining the taper rule to reconcile the first routing rule and the first rule, wherein the relation indicates a conflict between the first rule and the first routing rule.

13. The computer implemented method of claim 12, the process further comprising:

identifying or determining a first spacetile layer for the first rule;

identifying or determining a second spacetile layer for the first routing rule;

identifying or determining a via spacetile layer for the first spacetile layer and the second spacetile layer; and

aggregating the one or more spacetiles from the first spacetile layer and the second spacetile layer into the via spacetile layer.

14. The computer implemented method of claim 12, the process further comprising:

determining whether or not a taper rule is allowed in implementing the at least a part of the net;

determining whether wrong-way tracks are to be used to implement the at least a part of the net;

identifying or determining a cost mechanism; and

associating a cost with a physical implementation, which violates the first rule or the first routing rule, of the at least a part of the net.

15. The computer implemented method of claim 14, the process further comprising:

identifying or determining a first spacetile layer for the first rule;

identifying or determining a second spacetile layer for the first routing rule;

identifying or determining a via spacetile layer for the first spacetile layer and the second spacetile layer; and

aggregating the one or more spacetiles from the first spacetile layer and the second spacetile layer into the via spacetile layer.

16. The computer implemented method of claim 14, the process further comprising:

marking the at least a spacetile as satisfying the first routing rule, wherein the at least a spacetile is determined not to satisfy the first routing rule.

17. The computer implemented method of claim 1, the process further comprising:

identifying or determining a soft transition rule for transition between a first portion of an electronic design associated with one or more hard rules; and

identifying or determining a second portion of the electronic design associated with one or more soft rules or no rules at all in the electronic design.

18. The computer implemented method of claim 17, the process further comprising:

identifying or determining a transition region to which the soft transition rule applies, wherein the soft transition region is associated with the first portion and the second portion; and

implementing at least a portion of the net including the shape in both the first portion and the second portion by using at least the transition region.

19. The computer implemented method of claim 17, the process further comprising at least one of:

determining whether gridded, gridless, tracked, or trackless routing methodology is used to implement the at least a part of the first portion and the second portion;

determining whether or not wrong-way routing is permitted in implementing the at least the part of the first portion and the second portion; and

determining a via spacetile layer.

20. The computer implemented method of claim 19, the act of determining the via spacetile layer comprising:

performing a spacetile punch process for the first region to create a first set of one or more spacetiles;

identifying a second set of zero or more spacetiles from the second portion;

aggregating the first set of spacetiles and the second set of zero or more spacetiles to form one or more spacetiles; and

incorporating the one or more spacetiles into the via spacetile layer at corresponding locations.

21. The computer implemented method of claim 17, the process further comprising at least one of:

determining whether or not an object for which interconnection is desired is aligned with a track to satisfy at least one rule of the one or more hard rules and the one or more soft rules; and

identifying or determining a cost for a physical implementation failing to satisfy one of the one or more soft rules.

22. A system for implementing electronic design using flexible routing tracks, comprising:

a computing system having at least one processor or at least one processor core that is to;

identify, with a track pattern manipulation mechanism including or functioning in conjunction with at least one processor or at least one processor core of a computing system, a track pattern having multiple tracks and associated with a first routing rule for implementing at least a part of a net including a shape in a first region on a first layer, wherein the shape is associated with a first rule;

identify or create one or more spacetiles based at least in part upon the shape; and

implement the at least a part of the net including the shape by using at least a spacetile of the one or more spacetiles as a search probe for implementation of the at least part of the net, wherein the at least one spacetile overlaps in part or in whole with at least the shape.

23. The system of claim 22, wherein the at least one processor or at least one processor core is further to:

determine whether or not wrong-way tracks are to be used in implementing the at least a part of the net including the shape; and

identify a spacetile as an area-based search probe from the one or more spacetiles, wherein the act of implementing the at least a part of the net is performed by further using the area-based search probe.

24. The system of claim 23, wherein the at least one processor or at least one processor core is further to:

identify or creating a via spacetile layer for the first layer and a second layer immediately neighboring the first layer, wherein

the wrong-way tracks are disallowed in implementing the at least a part of the net including the shape; and

identify the one or more spacetiles for the via spacetile layer by using at least one or more geometric components of the shape.

25. The system of claim 24, wherein the at least one processor or the at least one processor core is further to:

perform a spacetile punch process for the at least one or more geometric components of the shape to create a first set of spacetiles;

identify a second set of zero or more spacetiles from the second layer;

aggregate the first set of spacetiles and the second set of zero or more spacetiles to form the one or more spacetiles; and

incorporate the one or more spacetiles into the via spacetile layer at corresponding locations.

26. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a method for implementing electronic design using flexible routing tracks, the method comprising:

identifying with a track pattern manipulation mechanism including or functioning in conjunction with at least one processor or at least one processor core of a computing system, a track pattern having multiple tracks and associated with a first routing rule for implementing at least a part of a net including a shape in a first region on a first layer, wherein the shape is associated with a first rule;

identifying or creating one or more spacetiles based at least in part upon the shape; and

implementing the at least a part of the net including the shape by using at least a spacetile of the one or more spacetiles as a search probe for implementation of the at least part of the net, wherein the at least one spacetile overlaps in part or in whole with at least the shape.

27. The article of manufacture of claim 26, the process further comprising:

determining a relation between the shape or a geometric component of the shape and at least one track of the multiple tracks, wherein the relation indicates whether or not the shape or the geometric component of the shape is aligned with the at least one track of the multiple tracks.

28. The article of manufacture of claim 27, the process further comprising:

determining whether wrong-way tracks are to be used to implement the at least a part of the net;

identifying a spacetile as a search probe from the one or more spacetiles; and

performing an area-based search for implementation solutions by using at least the search probe, wherein the act of implementing the at least a part of the net is performed by further using at least some of the implementation solutions.

29. The article of manufacture of claim 27, the process further comprising:

determine whether or not a taper rule is allowed in implementing the at least a part of the net;

determine whether wrong-way tracks are to be used to implement the at least a part of the net; and

identify or determine the taper rule to reconcile the first routing rule and the first rule, wherein the relation indicates a conflict between the first rule and the first routing rule.

30. The article of manufacture of claim 27, the process further comprising:

determine whether or not a taper rule is allowed in implementing the at least a part of the net;

determine whether wrong-way tracks are to be used to implement the at least a part of the net;

identify or determine a cost mechanism; and

associate a cost with a physical implementation, which violates the first rule or the first routing rule, of the at least a part of the net.