Liquid crystal display using depletion-mode transistors

• US 9,214,127 B2
• Filed: 07/09/2013
• Issued: 12/15/2015
• Est. Priority Date: 07/09/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Jamshidi-Roudbari, Abbas, Yu, Cheng-Ho, Bae, Hopil, Chang, Shih Chang, Chang, Ting-Kuo
• Primary Examiner(s): Dharia, Prabodh M
• Application Number:
  US13/937,825
• Publication Number:
  US 20150015559A1
• Time in Patent Office: 889 Days
• Field of Search: 345/90, 345/103, 345204-215, 345/690, 257/48, 315/169.1, 349/38
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/0245 Clearing or presetting the whole screen independently of waveforms, e.g. on power-on G09G2310/063 takes precedence
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2320/0204 Compensation of DC component across the pixels in flat panels
• CPC Class Codes: G09G 2320/0266 Reduction of sub-frame artefacts
• CPC Class Codes: G09G 2330/027 Arrangements or methods related to powering off a display
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

Methods and devices employing charge removal circuitry are provided to reduce or eliminate artifacts due to a bias voltage remaining on an electronic display after the display is turned off. In one example, a method may include connecting a pixel electrode of a display to ground through charge removal circuitry while the display is off (e.g., using depletion-mode transistors that are active when gates of the depletion-mode transistors are provided a ground voltage). When a corresponding common electrode is also connected to ground, a voltage difference between the pixel electrode and common electrode may be reduced or eliminated, preventing a bias voltage from causing display artifacts in the pixel.

Claims

1. A method for reducing visual artifacts in a display, comprising:

turning off the display; and

in response to turning off the display;

connecting a pixel electrode of the pixel of the display to ground; and

maintaining using a depletion-mode transistor the connection of the pixel electrode of the pixel of the display to ground while the display is off, wherein the depletion-mode transistor maintains the connection while a gate of the depletion-mode transistor is connected to ground, wherein the maintained connection is configured to reduce or eliminate a voltage difference across a liquid crystal cell of the pixel while the display is off to reduce or eliminate visual artifacts when the display is turned back on;

wherein a common electrode of the pixel of the display has a voltage of substantially ground when the display is turned off.

2. The method of claim 1, wherein connecting the pixel electrode of the pixel of the display to ground comprises:

connecting a data line coupled to the depletion-mode transistor to ground, wherein the depletion-mode transistor comprises a thin film transistor; and

connecting the thin film transistor of the pixel to the data line; and

wherein maintaining the connection of the pixel electrode of the pixel of the display to ground while the display is off comprises;

maintaining the connection of the data line to ground while the display is off; and

maintaining the connection of the depletion-mode transistor to the data line while the display is off.

3. The method of claim 2, comprising:

connecting demultiplexer circuitry coupled to the data line to ground; and

maintaining a conductivity of the demultiplexer while the display is off to maintain the connection of the data line to ground via the demultiplexer circuitry.

4. The method of claim 2, wherein the data line is connected to ground via charge removal circuitry coupled to demultiplexer circuitry coupled to the data line and wherein the connection of the data line to ground is maintained by maintaining the connection to ground through the charge removal circuitry and the demultiplexer circuitry while the display is off.

5. The method of claim 2, wherein the data line is connected to ground through charge removal circuitry coupled directly to the data line and wherein the connection of the data line to ground is maintained by maintaining the connection to ground through the charge removal circuitry while the display is off.

6. The method of claim 1, wherein connecting the pixel electrode of the pixel of the display to ground and maintaining the connection of the pixel electrode of the pixel of the display to ground while the display is off comprises connecting the pixel electrode of the pixel of the display to ground via one or more depletion-mode transistors that are active when the display is off.

7. An electronic display comprising:

a plurality of pixels, each pixel comprising;

a common electrode;

a pixel electrode;

a liquid crystal cell; and

a depletion-mode transistor configured to couple the pixel electrode while a gate of the depletion-mode transistor is connected to approximately 0V;

a common voltage source configured to supply a common voltage to the common electrodes of the pixels;

a gate driver configured to supply activation signals to the pixels to activate the pixels;

a source driver configured to supply data signals to the pixel electrodes when the pixels are activated; and

charge removal circuitry configured to connect each pixel electrode to ground while the electronic display is turned off, wherein the charge removal circuitry is configured to reduce or eliminate a voltage difference across the liquid crystal cells of the plurality of pixels while the display is off to reduce or eliminate visual artifacts when the display is turned back on.

8. The electronic display of claim 7, wherein the charge removal circuitry is configured to dissipate a kickback voltage occurring when the electronic display is turned off.

9. The electronic display of claim 7, wherein the charge removal circuitry comprises one or more depletion-mode transistors.

10. The electronic display of claim 7, wherein the source driver is configured to provide one or more ground connections to the pixel electrodes via the charge removal circuitry while the display is off.

11. The electronic display of claim 7, comprising demultiplexer circuitry comprising depletion-mode transistors, wherein the demultiplexer circuitry is located between the charge removal circuitry and the pixels and the demultiplexer circuitry is configured to maintain an electrical connection between the charge removal circuitry and the pixels while the display is off.

12. The electronic display of claim 7, comprising demultiplexer circuitry comprising enhancement mode transistors, wherein the charge removal circuitry is coupled directly to the data lines to enable the charge removal circuitry to connect each pixel to ground while the display is off and the demultiplexer circuitry is configured not to enable an electrical connection while the display is off.

13. The electronic display of claim 7, comprising one or more traces configured to connect the charge removal circuitry to a ground source.

14. An electronic device comprising:

an electronic display comprising;

a plurality of pixels, each pixel comprising;

a liquid crystal cell;

a pixel electrode; and

a depletion-mode thin film transistor that controls access to the pixel electrode that couples the pixel electrode to ground when a gate of the depletion-mode thin film transistor is connected to a ground voltage; and

charge removal circuitry comprising a plurality of depletion-mode transistors configured to connect the pixel electrodes to ground while the electronic display is turned off, wherein the charge removal circuitry is configured to reduce or eliminate a voltage difference across the liquid crystal cells of the plurality of pixels while the display is off to reduce or eliminate visual artifacts when the display is turned back on.

15. The electronic device of claim 14, wherein the charge removal circuitry is also configured to enable an integrity of the plurality of pixels to be tested during manufacture of the electronic display.

16. The electronic device of claim 14, wherein the electronic device comprises a handheld electronic device, a portable telephone, a notebook computer, a desktop computer, a media playback device, or any combination thereof.

17. A method for manufacturing an electronic display, the method comprising:

forming a plurality of enhancement mode transistors in a semiconductor substrate;

masking the first plurality of enhancement mode transistors; and

forming a plurality of depletion-mode transistors in the semiconductor substrate, wherein the depletion-mode transistors are configured to couple pixel electrodes of pixels of the display to ground when gates of the depletion-mode transistors are connected to approximately 0V, wherein the depletion mode transistors are configured to reduce or eliminate a voltage difference across liquid crystal cells of the pixels of the display while the display is off to reduce or eliminate visual artifacts when the display is turned back on.

18. The method of claim 17, wherein forming the plurality of enhancement mode transistors comprises forming transistors used by demultiplexer circuitry of the electronic display.

19. The method of claim 17, wherein forming the plurality of depletion-mode transistors comprises forming transistors used by charge removal circuitry and an active area of the electronic display.

20. A pixel array of an electronic display comprising:

charge removal circuitry comprising charge removal depletion-mode transistors configured to connect to ground while the electronic display is off; and

an active area of the electronic display comprises a plurality of unit pixels each having a pixel electrode, a liquid crystal cell, and a depletion-mode access transistor, wherein the depletion-mode access transistor is configured to electrically connect the pixel electrode to a data line while the electronic display is off while a gate of the depletion-mode access transistor receives a ground voltage, and wherein each data line is configured to electrically connect to ground while the electronic display is off via the charge removal depletion-mode transistors connected to ground while the electronic display is off, wherein the charge removal circuitry is configured to reduce or eliminate a voltage difference across the liquid crystal cells while the display is off to reduce or eliminate visual artifacts when the display is turned back on.

21. The pixel array of claim 20, wherein the access and charge removal depletion-mode transistors comprise thin film transistors.

22. The pixel array of claim 20, comprising demultiplexer circuitry located between the active area and the charge removal circuitry, wherein the demultiplexer circuitry comprises depletion-mode transistors that are configured to electrically connect each data line to the charge removal circuitry while the electronic display is off.

23. An electronic display comprising:

a pixel comprising;

a pixel electrode;

a liquid crystal cell; and

a depletion-mode thin-film-transistor that couples the pixel electrode to ground while a gate of the depletion-mode thin-film transistor receives a ground voltage, wherein the depletion-mode thin-film transistor is configured to reduce or eliminate a voltage difference across the liquid crystal cell while the display is off to reduce or eliminate visual artifacts when the display is turned back on.