Dynamic erase depth for improved endurance of non-volatile memory

• US 9,214,240 B2
• Filed: 03/03/2014
• Issued: 12/15/2015
• Est. Priority Date: 03/04/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dutta, Deepanshu, Lai, Chun-Hung, Lee, Shih-Chung, Oowada, Ken, Higashitani, Masaaki
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US14/195,265
• Publication Number:
  US 20140247666A1
• Time in Patent Office: 652 Days
• Field of Search: 365/185.17, 365/185.19, 365/185.21, 365/185.22, 365/185.23, 365/185.24, 365/185.29, 365/218
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth.

Claims

1. A method of operating non-volatile storage, the method comprising:

erasing a group of non-volatile storage elements;

programming a set of the non-volatile storage elements in the group after erasing the group;

determining an upper tail of an erase distribution of non-volatile storage elements in the set after the programming;

establishing an erase depth for erasing the group of non-volatile storage elements based on the upper tail; and

erasing the group of non-volatile storage elements based on the established erase depth.

2. The method of claim 1, wherein the establishing an erase depth for erasing the group of non-volatile storage elements based on the upper tail comprises:

establishing a shallower erase depth when the upper tail is higher and a deeper erase depth when the upper tail is lower.

3. The method of claim 1, wherein the determining an upper tail of an erase distribution of non-volatile storage elements in the set after the programming comprises:

determining erase-state to A-state fails of non-volatile storage elements in the set after the programming.

4. The method of claim 3, wherein the establishing an erase depth for erasing the group of non-volatile storage elements based on the upper tail comprises:

establishing a shallower erase depth when the amount of erase state to A-state fails is higher and a deeper erase depth when an amount of erase state to A-state fails is lower.

5. The method of claim 1, wherein the determining an upper tail of an erase distribution of non-volatile storage elements in the set after the programming comprises:

applying one or more reference voltages to gates of non-volatile storage elements in the set that were intended to be in an erased state after the programming, the one or more reference voltages are near an A-state read reference level;

sensing whether the non-volatile storage elements in set that were intended to be in an erased state after the programming conduct a current in response to the respective reference voltages; and

selecting the highest reference voltage for which the number of non-volatile storage elements in the set that were intended to be in the erased state that conduct a current is below a threshold number.

6. The method of claim 1, wherein erasing the group of non-volatile storage elements based on the established erase depth comprises:

erasing the group of non-volatile storage elements using an erase verify level that is based on the erase depth.

7. The method of claim 1, wherein erasing the group of non-volatile storage elements based on the established erase depth comprises:

erasing the group of non-volatile storage elements using a number of erase pulses after erase verify passes that depend on the erase depth.

8. The method of claim 1, wherein the programming a set of the non-volatile storage elements in the group comprises programming non-volatile storage elements associated with a first word line in a block, and further comprising:

programming a second word line in the block after programming the first word line;

storing information based on determining the upper tail of the erase distribution for the first word line, the information is stored in one or more non-volatile storage elements associated with the second word line when programming the second word line; and

accessing the stored information from the one or more non-volatile storage elements associated with the second word line in order to establish the erase depth for erasing the group of non-volatile storage elements.

9. The method of claim 1, wherein the determining an upper tail of an erase distribution of non-volatile storage elements in the set after the programming comprises:

performing a first read operation of the non-volatile storage elements in the set at a first reference level;

performing a second read operation of the non-volatile storage elements in the set at a second reference level; and

determining how many of the non-volatile storage elements have a threshold voltage between the first reference level and the second reference level based on the first read operation and the second read operation.

10. A non-volatile storage device comprising:

a group of non-volatile storage elements; and

one or more managing circuits in communication with the group of non-volatile storage elements, the one or more managing circuits erase the group of non-volatile storage elements, the one or more managing circuits program a set of the non-volatile storage elements in the group after erasing the group, the one or more managing circuits determine an upper tail of an erase distribution of non-volatile storage elements in the set after the programming, the one or more managing circuits establish an erase depth for erasing the group of non-volatile storage elements based on the upper tail, the one or more managing circuits erase the group using the established erase depth.

11. The non-volatile storage device of claim 10, wherein the one or more managing circuits establish a shallower erase depth when the upper tail is higher and a deeper erase depth when the upper tail is lower.

12. The non-volatile storage device of claim 10, wherein when the one or more managing circuits determine the upper tail of the erase distribution of non-volatile storage elements in the set after the programming, the one or more managing circuits determine erase state to A-state fails of non-volatile storage elements in the set after the programming, wherein the one or more managing circuits establish a more shallow erase depth when an amount of erase state to A-state fails is higher and a deeper erase depth when the amount of erase state to A-state fails is lower.

13. The non-volatile storage device of claim 10, wherein when the one or more managing circuits determine the upper tail of the erase distribution of non-volatile storage elements in the set after the programming, the one or more managing circuits perform one or more reads of non-volatile storage elements in set that were intended to be in an erased state after the programming at corresponding reference levels near an A-state read reference level, the one or more managing circuits determine the highest reference level for which the number of erase state to A-state fails is below a threshold number.

14. The non-volatile storage device of claim 10, wherein the one or more managing circuits save the established erase verify level in a block that is associated with the group of non-volatile storage elements for a future erase operation.

15. The non-volatile storage device of claim 10, wherein the group of non-volatile storage elements are part of a 3D memory array.

16. A non-volatile storage device comprising:

a group of non-volatile storage elements arranged as NAND strings;

a plurality of word lines associated with the group of non-volatile storage elements; and

one or more managing circuits in communication with the group of non-volatile storage elements, the one or more managing circuits erase the group of non-volatile storage elements, the one or more managing circuits program non-volatile storage elements in the group that are associated with a first word line of the plurality of word lines after erasing the group, the one or more managing circuits determine erase state to A-state fails of non-volatile storage elements in the group of non-volatile storage elements associated with the first word line after the programming, the one or more managing circuits establish an erase verify level for erasing the group of non-volatile storage elements based on the erase state to A-state fails, the one or more managing circuits erase the group based on the established erase verify level.

17. The non-volatile storage device of claim 16, wherein the determining erase state to A-state fails of non-volatile storage elements comprises:

sensing non-volatile storage elements associated with the first word line that were intended to stay erased after the programming; and

determining how many of the non-volatile storage elements that were to intended to stay erased have a threshold voltage that is above a read reference level of the A-state.

18. The non-volatile storage device of claim 16, wherein the determining erase state to A-state fails of non-volatile storage elements comprises:

sense non-volatile storage elements associated with the first word line that were intended to stay erased after the programming at a plurality of reference levels just above a read reference level of the A-state; and

determine the highest of the plurality of reference levels for which the number of erase state to A-state fails is less than a threshold number.

19. A method of operating non-volatile storage that includes a group of non-volatile storage elements, the method comprising:

programming a set of the non-volatile storage elements in the group;

determining how many program loops or a magnitude of a final programming voltage it takes to complete the programming; and

establishing an erase depth for erasing the group of non-volatile storage elements based on how many program loops or a magnitude of a final programming voltage it takes to complete the programming.

20. A 3D non-volatile storage device comprising:

a plurality of word line layers;

a plurality of insulator layers alternating with the word line layers in a stack;

a plurality of non-volatile storage element strings, each non-volatile storage element string comprises a plurality of non-volatile storage elements, each of the non-volatile storage elements is associated with one of the plurality of word line layers; and

one or more managing circuits in communication with plurality of non-volatile storage elements, the one or more managing circuits erase a group of the non-volatile storage elements, the one or more managing circuits program a set of the non-volatile storage elements in the group after erasing the group, the one or more managing circuits determine an upper tail of an erase distribution of non-volatile storage elements in the set after the programming, the one or more managing circuits establish an erase depth for erasing the group of non-volatile storage elements based on the upper tail, the one or more managing circuits erase the group using the established erase depth.