Three-dimensional nonvolatile memory and method of fabrication

• US 9,214,243 B2
• Filed: 05/06/2014
• Issued: 12/15/2015
• Est. Priority Date: 11/16/1998
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Johnson, Mark G., Lee, Thomas H., Subramanian, Vivek, Farmwald, Paul Michael, Cleeves, James M.
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US14/270,409
• Publication Number:
  US 20140239248A1
• Time in Patent Office: 588 Days
• Field of Search: 365/189.15, 365/200, 365/205, 365/207, 365/230.03, 365/230.06, 365/51, 365/63, 365/94
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.

Claims

1. A three-dimensional memory comprising:

a first memory level comprising a first pillar-shaped memory cell comprising a first steering element coupled in series with and vertically stacked above or below a first non-volatile re-writable state change element; and

a second memory level monolithically formed above the first memory level, the second memory level comprising a second pillar-shaped memory cell comprising a second steering element coupled in series with and vertically stacked above or below a second non-volatile re-writable state change element.

2. The three-dimensional memory of claim 1, wherein each of the first and second steering elements comprises a p-n diode, a p-i-n diode or a Schottky diode.

3. The three-dimensional memory of claim 1, wherein each of the first and second state change elements comprises a reversible resistance-switching element.

4. The three-dimensional memory of claim 1, wherein each of the first and second state change elements comprises more than two resistance states.

5. The three-dimensional memory of claim 1, wherein each of the first and second state change elements comprises more than two memory states.

6. A three-dimensional memory comprising:

a first memory array comprising a plurality of pillar-shaped first memory cells, each first memory cell comprising a first steering element coupled in series with and vertically stacked above or below a first non-volatile re-writable state change element; and

a second memory array monolithically formed above the first memory array, the second memory level comprising a plurality of pillar-shaped second memory cells, each second memory cell comprising a second steering element coupled in series with and vertically stacked above or below a second non-volatile re-writable state change element.

7. The three-dimensional memory of claim 6, wherein each of the first and second steering elements comprises a p-n diode, a p-i-n diode or a Schottky diode.

8. The three-dimensional memory of claim 6, wherein each of the first and second state change elements comprises a reversible resistance-switching element.

9. The three-dimensional memory of claim 6, wherein each of the first and second state change elements comprises more than two resistance states.

10. The three-dimensional memory of claim 6, wherein each of the first and second state change elements comprises more than two memory states.

11. A three-dimensional memory comprising:

a first memory cell comprising a first steering element coupled in series with a first non-volatile re-writable state change element; and

a second memory cell formed above the first memory cell, the second memory cell comprising a second steering element coupled in series with a second non-volatile re-writable state change element,

wherein the first memory cell and the second memory cell each comprise an active area disposed above a substrate.

12. The three-dimensional memory of claim 11, wherein the substrate comprises silicon.

13. The three-dimensional memory of claim 11, wherein each of the first and second state change elements comprises a reversible resistance-switching element.

14. The three-dimensional memory of claim 11, further comprising peripheral circuitry built in the substrate.

15. The three-dimensional memory of claim 14, wherein the peripheral circuitry comprises a sense amplifier.

16. The three-dimensional memory of claim 14, wherein the peripheral circuitry comprises a write driver.