Method for forming through-silicon via (TSV) with diffused isolation well

• US 9,214,390 B2
• Filed: 06/10/2014
• Issued: 12/15/2015
• Est. Priority Date: 06/24/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chi-Yeh
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): ESKRIDGE, CORY W
• Application Number:
  US14/301,133
• Publication Number:
  US 20140295655A1
• Time in Patent Office: 553 Days
• Field of Search: 257/276, 257/621, 257/698, 257/E23.067, 438/667
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance.

Claims

1. A method for forming a through silicon via (TSV) in an integrated circuit, said method comprising:

providing a substrate of a first dopant impurity type and including a through silicon via (TSV) extending downwardly from a top surface of said substrate and including sidewalls;

thermally diffusing dopant impurities of a second dopant impurity type into said sidewalls so as to form a well region in said substrate surrounding said TSV;

after said thermally diffusing, performing a further thermal diffusion operation that introduces dopants of said first dopant impurity type into said sidewalls such that said well region includes an outer portion of said second dopant impurity type and an inner portion of said first dopant impurity type;

thermally oxidizing said sidewalls after said further thermal diffusion operation; and

filling said TSV with a conductive plug.

2. The method as in claim 1, further comprising polishing an opposed bottom surface of said substrate such that said TSV and said conductive plug extend from said top surface to said opposed bottom surface.

3. The method as in claim 1, wherein said providing a substrate includes said TSV extending from said top surface to a bottom surface of said substrate.

4. The method as in claim 3, wherein said substrate includes a hard mask on said top surface, said hard mask comprising nitride or oxynitride, and said TSV extends through said hardmask.

5. The method as in claim 1, wherein said inner portion comprises a high concentration region of said first dopant impurity type having a first dopant concentration greater than a second dopant concentration in said outer portion of said second dopant impurity type.

6. The method as in claim 1, wherein said first impurity type comprises N-type and said second impurity type comprises P-type.

7. The method as in claim 1, wherein said providing a substrate comprises said substrate including semiconductor devices thereon and further comprising, after said filling said TSV with a conductive plug, carrying out further processing operations to interconnect said semiconductor devices.

8. The method as in claim 1, wherein said thermally diffusing dopant impurities of a second dopant impurity type into said sidewalls thereby forms said well region having a dopant concentration that increases along a direction toward said TSV.

9. A method for forming a through silicon via (TSV) in an integrated circuit, said method comprising:

providing a substrate of a first dopant impurity type and including a through silicon via (TSV) extending from a top surface of said substrate through a bottom surface of said substrate and including sidewalls;

thermally diffusing dopant impurities of a second dopant impurity type into said sidewalls thereby forming a well region in said substrate surrounding said TSV;

performing a further thermal diffusion operation introducing dopants of said first dopant impurity type into said sidewalls such that said well region includes an outer portion of said second dopant impurity type and an inner portion of said first dopant impurity type;

thermally oxidizing said sidewalls; and

filling said TSV with a conductive plug.

10. The method as in claim 9, wherein said first impurity type comprises N-type and said second impurity type comprises P-type.

11. The method as in claim 9, wherein said TSV includes a width of about 5-15 microns, said well region includes a width of about 2-20 microns, said conductive plug comprises one of copper and tungsten, and further comprising forming a contact pad contacting said conductive plug, on said bottom surface.

12. The method as in claim 9, wherein said inner portion comprises a high concentration region having a first dopant concentration greater than a second dopant concentration in said outer portion.

13. A method for forming a through silicon via (TSV) in an integrated circuit, said method comprising:

providing a substrate of a first dopant impurity type and including a through silicon via (TSV) extending from a top surface of said substrate through an opposed bottom surface of said substrate and including sidewalls;

thermally diffusing dopant impurities of a first species of a second dopant impurity type into said sidewalls to form a well region;

performing a further thermal diffusion operation introducing dopant impurities of a second species of said second impurity type into said sidewalls to form an inner portion formed of said second species of said second dopant impurity type that surrounds said TSV and surrounded by an outer portion formed of said first species of said second dopant impurity type; and

filling said TSV with a conductive material.

14. The method as in claim 13, further comprising thermally oxidizing said sidewalls before said filling said TSV with a conductive material.

15. The method as in claim 13, wherein said inner portion comprises a high concentration region having a first dopant concentration greater than a second dopant concentration in said outer portion.

16. The method as in claim 13, further comprising a second TSV extending from said top surface of said substrate through said opposed bottom surface of said substrate, and

wherein said thermally diffusing includes said second TSV within said well region and said performing a further thermal diffusion operation introduces said dopant impurities of said second species of said second impurity type into second sidewalls surrounding said second TSV.

17. The method as in claim 13, wherein said first species of said second dopant impurity type comprises arsenic and said second species of said second dopant impurity type comprises phosphorous.

18. The method as in claim 13, wherein said first species of said second dopant impurity type comprises phosphorous and said second species of said second dopant impurity type comprises arsenic.

19. A method for forming a through silicon via (TSV) in an integrated circuit, said method comprising:

providing a substrate of a first dopant impurity type and including a through silicon via (TSV) extending downwardly from a top surface of said substrate and including sidewalls;

thermally diffusing a first species of a second dopant impurity type into said sidewalls, so as to form a well region in said substrate surrounding said TSV;

after said thermally diffusing, performing a further thermal diffusion operation comprising thermally diffusing a second species of said second dopant impurity type into said sidewalls such that said well region includes an outer portion of said first species of said second dopant impurity type and an inner portion of said second species of said second dopant impurity type;

thermally oxidizing said sidewalls after said further thermal diffusion operation; and

filling said TSV with a conductive plug.

20. The method as in claim 19, further comprising polishing a bottom surface opposite said top surface of said substrate such that said TSV and said conductive plug extend from said top surface to said opposed bottom surface.

21. The method as in claim 19, wherein said providing a substrate includes said TSV extending from said top surface to a bottom surface of said substrate.

22. The method as in claim 21, wherein said substrate includes a hard mask on said top surface, said hard mask comprising a nitride or an oxynitride, and said TSV extending through said hardmask.

23. The method as in claim 19, wherein said second dopant impurity type is n-type.

24. The method as in claim 19, wherein said first species comprises phosphorus and said second species comprises arsenic.

25. The method as in claim 24, wherein a concentration of arsenic in said inner portion is greater than a concentration of phosphorus in said outer portion.