Trenched power MOSFET with enhanced breakdown voltage and fabrication method thereof
First Claim
1. A fabrication method of a trenched power semiconductor device with enhanced breakdown voltage at least comprising steps of:
- (a) providing a substrate;
(b) forming at least two gate trenches in the substrate;
(c) forming a first dielectric layer lining inner surfaces of the gate trenches;
(d) forming a first polysilicon structure in the gate trenches;
(e) forming at least a first trench, wherein the first trench is positioned between the neighboring gate trenches;
(f) forming a second polysilicon structure of a first conductive type in a lower portion of the first trench, wherein the second polysilicon structure is in contact with the portion of the substrate that is surrounding the first trench;
(g) after the step of forming the second polysilicon structure of the first conductive type, forming a dielectric structure in the first trench, wherein the dielectric structure at least extends upward to the body region;
(h) forming a body region of the first conductive type between the gate trenches, wherein the first trench extends to the substrate below the body region, and the second polysilicon structure is spaced from the body region with a predetermined distance;
(i) forming a source region of a second conductive type in an upper portion of the body region;
(j) forming an interlayer dielectric layer on the first polysilicon structure to define a source contact window aligned to the first trench;
(k) forming at least a heavily doped region of the first conductive type in the body region; and
(l) forming a source metal layer in the source contact window for electrically connecting to the heavily doped region and the source region.
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Accused Products
Abstract
A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region.
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Citations
16 Claims
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1. A fabrication method of a trenched power semiconductor device with enhanced breakdown voltage at least comprising steps of:
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(a) providing a substrate; (b) forming at least two gate trenches in the substrate; (c) forming a first dielectric layer lining inner surfaces of the gate trenches; (d) forming a first polysilicon structure in the gate trenches; (e) forming at least a first trench, wherein the first trench is positioned between the neighboring gate trenches; (f) forming a second polysilicon structure of a first conductive type in a lower portion of the first trench, wherein the second polysilicon structure is in contact with the portion of the substrate that is surrounding the first trench; (g) after the step of forming the second polysilicon structure of the first conductive type, forming a dielectric structure in the first trench, wherein the dielectric structure at least extends upward to the body region; (h) forming a body region of the first conductive type between the gate trenches, wherein the first trench extends to the substrate below the body region, and the second polysilicon structure is spaced from the body region with a predetermined distance; (i) forming a source region of a second conductive type in an upper portion of the body region; (j) forming an interlayer dielectric layer on the first polysilicon structure to define a source contact window aligned to the first trench; (k) forming at least a heavily doped region of the first conductive type in the body region; and (l) forming a source metal layer in the source contact window for electrically connecting to the heavily doped region and the source region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A fabrication method of a trenched power semiconductor device with enhanced breakdown voltage at least comprising steps of:
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providing a substrate; forming at least a first trench in the substrate; forming a second polysilicon structure of a first conductive type in a lower portion of the first trench, wherein the second polysilicon structure is in contact with the portion of the substrate that is surrounding the first trench; disposing a first dielectric layer over the second polysilicon structure and the substrate; forming at least two gate trenches respectively in the portions of the substrate positioned at two sides of the first trench; removing a portion of the first dielectric layer; forming a second dielectric layer lining inner surfaces of the gate trenches; forming a first polysilicon structure in the gate trenches; forming a body region of the first conductive type in the substrate; forming a source region of a second conductive type in an upper portion of the body region, wherein the step of forming the body region of the first conductive type and the step of forming the source region of the second conductive type are prior to the step of forming the first trench; and forming at least a heavily doped region of the first conductive type in the body region, wherein the body region is positioned between the gate trenches, the first trench extends to the substrate below the body region, and the second polysilicon structure is spaced from the body region with a predetermined distance. - View Dependent Claims (10, 11, 12)
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13. A fabrication method of a trenched power semiconductor device with enhanced breakdown voltage at least comprising steps of:
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providing a substrate; simultaneously forming at least a first trench and at least two gate trenches in the substrate, wherein the at least two gate trenches are respectively positioned in the portions of the substrate at two sides of the first trench; forming a first dielectric layer lining inner surfaces of the first trench and the gate trenches; forming a first polysilicon structure in the first trench and the gate trenches; forming a body region of a first conductive type in the substrate; forming a source region of a second conductive type in an upper portion of the body region; removing the first polysilicon structure in the first trench; after the step of removing the first polysilicon structure in the first trench, forming a second polysilicon structure in the first trench, wherein the second polysilicon structure is in contact with the portion of the substrate that is surrounding the first trench; filling a dielectric structure in the first trench; forming an interlayer dielectric layer to shield the first polysilicon structure in the gate trenches, wherein the interlayer dielectric layer has an open aligned to the first trench, and the open has a width greater than that of the first trench; forming a source contact window, wherein the open of the interlayer dielectric layer defines the range of the source contact window; forming at least a heavily doped region below the source contact window; and forming a metal layer filled into the source contact window. - View Dependent Claims (14, 15, 16)
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Specification