Trenched power MOSFET with enhanced breakdown voltage and fabrication method thereof

• US 9,214,531 B2
• Filed: 03/07/2013
• Issued: 12/15/2015
• Est. Priority Date: 08/13/2012
• Status: Active Grant

• Current Assignee: Super Group Semiconductor Co., Ltd.
• Original Assignee: Great Power Semiconductor Corp.
• Inventors: Yeh, Chun-Ying
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US13/788,087
• Publication Number:
  US 20140120670A1
• Time in Patent Office: 1,013 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region.

Claims

1. A fabrication method of a trenched power semiconductor device with enhanced breakdown voltage at least comprising steps of:

(a) providing a substrate;

(b) forming at least two gate trenches in the substrate;

(c) forming a first dielectric layer lining inner surfaces of the gate trenches;

(d) forming a first polysilicon structure in the gate trenches;

(e) forming at least a first trench, wherein the first trench is positioned between the neighboring gate trenches;

(f) forming a second polysilicon structure of a first conductive type in a lower portion of the first trench, wherein the second polysilicon structure is in contact with the portion of the substrate that is surrounding the first trench;

(g) after the step of forming the second polysilicon structure of the first conductive type, forming a dielectric structure in the first trench, wherein the dielectric structure at least extends upward to the body region;

(h) forming a body region of the first conductive type between the gate trenches, wherein the first trench extends to the substrate below the body region, and the second polysilicon structure is spaced from the body region with a predetermined distance;

(i) forming a source region of a second conductive type in an upper portion of the body region;

(j) forming an interlayer dielectric layer on the first polysilicon structure to define a source contact window aligned to the first trench;

(k) forming at least a heavily doped region of the first conductive type in the body region; and

(l) forming a source metal layer in the source contact window for electrically connecting to the heavily doped region and the source region.

2. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the step of forming the dielectric structure comprises:

forming a dielectric layer covering the interlayer dielectric layer and filling the first trench; and

removing a portion of the dielectric layer outside the first trench and expanding a width of the source contact window by etching.

3. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the steps of the forming the heavily doped region and the source region include two ion implantation steps for implanting dopants of the first conductive type and that of the second conductive type respectively, and implantation areas of the two ion implantation steps are partly overlapped for forming the heavily doped region and the source region alternatively arrayed on the body region.

4. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the step of forming the heavily doped region is to implant first conductive type dopants into the body region through the source contact window, and the heavily doped region is extended to the substrate below the body region.

5. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the step of forming the heavily doped region includes:

forming a heavily doped polysilicon structure on the dielectric structure; and

thermal diffusing dopants in the heavily doped polysilicon structure to the body region for forming the heavily doped region adjacent to the heavily doped polysilicon structure.

6. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the step of forming the first trench is later than the step of forming the source region in the upper portion of the body region, and the first trench penetrates the body region.

7. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, after the step of forming the second polysilicon structure, further comprising a step of forming a third polysilicon structure of the second conductive type in the first trench, and the third polysilicon structure being located above the second polysilicon structure and at least extended upward to the body region.

8. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, after the step of forming the second polysilicon structure of the first conductive type, further comprising a step of filling a metal plug in the first trench, and the metal plug being located above the second polysilicon structure and at least extended upward to the body region.

9. A fabrication method of a trenched power semiconductor device with enhanced breakdown voltage at least comprising steps of:

providing a substrate;

forming at least a first trench in the substrate;

forming a second polysilicon structure of a first conductive type in a lower portion of the first trench, wherein the second polysilicon structure is in contact with the portion of the substrate that is surrounding the first trench;

disposing a first dielectric layer over the second polysilicon structure and the substrate;

forming at least two gate trenches respectively in the portions of the substrate positioned at two sides of the first trench;

removing a portion of the first dielectric layer;

forming a second dielectric layer lining inner surfaces of the gate trenches;

forming a first polysilicon structure in the gate trenches;

forming a body region of the first conductive type in the substrate;

forming a source region of a second conductive type in an upper portion of the body region, wherein the step of forming the body region of the first conductive type and the step of forming the source region of the second conductive type are prior to the step of forming the first trench; and

forming at least a heavily doped region of the first conductive type in the body region, wherein the body region is positioned between the gate trenches, the first trench extends to the substrate below the body region, and the second polysilicon structure is spaced from the body region with a predetermined distance.

10. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 9, wherein the step of removing a portion of the first dielectric layer comprises a step of:

removing a portion of the first dielectric layer to leave a dielectric structure in the first trench.

11. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 9, wherein the step of removing a portion of the first dielectric layer comprises a step of:

removing a portion of the first dielectric layer that is filled in the first trench; and

the fabrication method of the trenched power semiconductor device with enhanced breakdown voltage further comprises a step of;

forming a third polysilicon structure of the second conductive type in the first trench, wherein the third polysilicon structure is positioned on the second polysilicon structure and extends upward to the body region.

12. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 9, wherein the step of removing a portion of the first dielectric layer comprises a step of:

removing a portion of the first dielectric layer that is filled in the first trench; and

the fabrication method of the trenched power semiconductor device with enhanced breakdown voltage further comprises a step of;

forming a metal plug in the first trench, wherein the metal plug is positioned on the second polysilicon structure and extends upward to the body region.

13. A fabrication method of a trenched power semiconductor device with enhanced breakdown voltage at least comprising steps of:

providing a substrate;

simultaneously forming at least a first trench and at least two gate trenches in the substrate, wherein the at least two gate trenches are respectively positioned in the portions of the substrate at two sides of the first trench;

forming a first dielectric layer lining inner surfaces of the first trench and the gate trenches;

forming a first polysilicon structure in the first trench and the gate trenches;

forming a body region of a first conductive type in the substrate;

forming a source region of a second conductive type in an upper portion of the body region;

removing the first polysilicon structure in the first trench;

after the step of removing the first polysilicon structure in the first trench, forming a second polysilicon structure in the first trench, wherein the second polysilicon structure is in contact with the portion of the substrate that is surrounding the first trench;

filling a dielectric structure in the first trench;

forming an interlayer dielectric layer to shield the first polysilicon structure in the gate trenches, wherein the interlayer dielectric layer has an open aligned to the first trench, and the open has a width greater than that of the first trench;

forming a source contact window, wherein the open of the interlayer dielectric layer defines the range of the source contact window;

forming at least a heavily doped region below the source contact window; and

forming a metal layer filled into the source contact window.

14. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 13, after the step of forming the source contact window and before the step of forming the heavily doped region, further comprising a step of:

forming a heavily doped polysilicon structure at the bottom of the source contact window, wherein the heavily doped region is formed surrounding the heavily doped polysilicon structure.

15. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 13, wherein the dielectric structure is protruded upward from the bottom surface of the source contact window, and the step of forming the heavily doped region below the source contact window comprises a step of:

forming the heavily doped region in the body region adjacent to the opposite sides of the dielectric structure.

16. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 13, wherein the source contact window is extended to a portion of the substrate below the body region such that the portion of the substrate below the body region is exposed, and the step of forming the heavily doped region below the source contact window comprises a step of:

forming the heavily doped region at the opposite sides of the source contact window.