Self-aligned contact for replacement gate devices

• US 9,214,541 B2
• Filed: 02/28/2013
• Issued: 12/15/2015
• Est. Priority Date: 12/02/2010
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Ramachandran, Ravikumar, Li, Ying, Wise, Richard S.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US13/780,912
• Publication Number:
  US 20130175587A1
• Time in Patent Office: 1,020 Days
• Field of Search: 257/410, 257/296, 257/304
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.

Claims

1. A semiconductor structure comprising:

a gate stack located on a semiconductor substrate, wherein said gate stack comprises, from top to bottom, a U-shaped work function metal portion, a U-shaped barrier metal portion and a gate conductor portion;

a planarization dielectric layer laterally surrounding said gate stack, wherein a top surface of said gate stack is recessed relative to a top surface of said planarization dielectric layer; and

an etch stop layer contiguously located on said recessed top surface of said gate stack and said top surface of said planarization dielectric layer, wherein said etch stop layer includes a first portion located on said planarization dielectric layer and a second portion located on said gate stack and having a vertically offset bottom surface relative to an interface between said planarization dielectric layer and said first portion.

2. The semiconductor structure of claim 1, further comprising a contact-level dielectric layer overlying said planarization dielectric layer.

3. The semiconductor structure of claim 2, further comprising a contact via structure extending through said contact-level dielectric layer, said etch stop layer, and said planarization dielectric layer.

4. The semiconductor structure of claim 3, wherein a portion of said contact via structure overlies said gate electrode and is vertically spaced by said second portion of said etch stop layer.

5. The semiconductor structure of claim 4, wherein said first portion and a center region of said second portion of said etch stop layer have a same composition and a same thickness.

6. The semiconductor structure of claim 5, wherein a peripheral region of said second portion has sidewalls that are vertically coincident with sidewalls of said gate stack, and extends from a level coplanar with a bottom surface of said center region of said second portion to a level coplanar with a top surface of said first portion.

7. The semiconductor structure of claim 4, wherein said etch stop layer comprises a dielectric material having a different composition than said contact-level dielectric layer and said planarization dielectric layer.

8. The semiconductor structure of claim 7, wherein said etch stop layer comprises a material having a chemical composition of SiC_xO_yH_z, SiN_wC_xO_yH_z, SiC_xH_z, or SiN_wC_xH_z, wherein each of w, x, y, and z independently has a value greater than 0 and less than 0.75.

9. The semiconductor structure of claim 8, wherein each of said contact-level dielectric layer and said planarization dielectric layer includes a material selected from undoped silicate glass (USG), doped silicate glass, silicon nitride, organsilicate glass (OSG), undoped silicon oxynitride, and doped silicon oxynitride.

10. The semiconductor structure of claim 4, further comprising a dielectric gate spacer laterally surrounding said gate stack and is laterally surrounded by said planarization dielectric layer.

11. The semiconductor structure of claim 10, wherein said contact via structure is spaced from said gate stack by said etch stop layer and said dielectric gate spacer.

12. The semiconductor structure of claim 10, wherein said contact via structure is in contact with an outer sidewall of said dielectric gate spacer.

13. The semiconductor structure of claim 12, further comprising a metal semiconductor alloy portion located on said semiconductor substrate and in contact with said contact via structure.

14. The semiconductor structure of claim 13, wherein said metal semiconductor alloy portion contacts a source region or a drain region of a field effect transistor.

15. The semiconductor structure of claim 10, wherein a top portion of said dielectric gate spacer protrudes above a topmost surface of said gate stack.

16. The semiconductor structure of claim 10, further comprising a U-shaped gate dielectric including a vertical portion that contacts a sidewall of said dielectric gate spacer.

17. The semiconductor structure of claim 16, wherein said U-shaped gate dielectric is in contact with a sidewall of said etch stop layer.

18. The semiconductor structure of claim 16, wherein all sidewall surfaces of said U-shaped gate dielectric contacts sidewalls of said dielectric gate spacer.

19. The semiconductor structure of claim 16, wherein said contact via structure contacts a top surface of said U-shaped gate dielectric.

20. The semiconductor structure of claim 16, wherein said U-shaped gate dielectric comprises a dielectric material having a dielectric constant greater than 8.0.