Source and body contact structure for trench-DMOS devices using polysilicon

• US 9,214,544 B2
• Filed: 04/18/2014
• Issued: 12/15/2015
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hbert, Franois, Bhalla, Anup
• Primary Examiner(s): Moore, Whitney T
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US14/256,843
• Publication Number:
  US 20140225188A1
• Time in Patent Office: 606 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A semiconductor device comprising:

a body region formed in an epitaxial layer;

a gate electrode formed in a trench in the body region and epitaxial layer;

a source region disposed on the body region next to the gate electrode;

a gate oxide disposed between the gate electrode and the source region, the body region and the epitaxial layer;

a drain region formed by a substrate disposed below a bottom of the gate electrode and below the body region;

an oxide disposed on top of the gate electrode and extending over a top portion of the source region;

a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide;

an exposed body contact region in an upper portion of the body region, adjacent to the doped polysilicon spacer, wherein the exposed body contact region has a top surface which is recessed below the bottom surface of the source region and spaced away from the source region by the doped Polysilicon spacer; and

a source metal layer disposed on the device such that the doped polysilicon spacer is in electrical contact with the source region and the source metal layer.

2. The semiconductor device of claim 1, wherein a portion of a top surface of the body region not underlying the source region is recessed to a lower level than a portion of the top surface of the body region underlying the source region.

3. The semiconductor device of claim 1, wherein the doped polysilicon spacer extends to a top portion of the source region.

4. The semiconductor device of claim 1, wherein the semiconductor device is an N-channel device.