Oxide semiconductor film and semiconductor device

• US 9,214,563 B2
• Filed: 07/22/2013
• Issued: 12/15/2015
• Est. Priority Date: 09/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakakura, Masayuki, Watanabe, Ryosuke, Sakata, Junichiro, Akimoto, Kengo, Miyanaga, Akiharu, Hirohashi, Takuya, Kishida, Hideyuki
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/947,334
• Publication Number:
  US 20130299827A1
• Time in Patent Office: 876 Days
• Field of Search: 257/43, 257/E21.476, 257/E29.296, 438/158
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2636 for heating, e.g. electron beam heating
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

Claims

1. An oxide semiconductor film comprising:

a first region and a second region,

wherein the oxide semiconductor film comprises In, Ga and Zn,

wherein a carbon concentration of the oxide semiconductor film is lower than 1×

10²¹ atoms/cm³,

wherein the first region is over the second region,

wherein the first region includes crystals which are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor film, and

wherein the second region includes nanocrystals.

2. The oxide semiconductor film according to claim 1, wherein a crystal structure of the crystals in the first region is represented by In₂Ga₂ZnO₇.

3. The oxide semiconductor film according to claim 1, wherein each of the nanocrystals has a particle size of greater than or equal to 1 nm and less than or equal to 20 nm.

4. A semiconductor device comprising:

a gate electrode layer;

an oxide semiconductor layer;

a gate insulating layer between the gate electrode layer and the oxide semiconductor layer;

a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; and

an oxide insulating layer over the source electrode layer and the drain electrode layer and in contact with a first region of a top surface of the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises a channel formation region,

wherein the oxide semiconductor layer comprises In, Ga and Zn,

wherein a carbon concentration of the oxide semiconductor layer is lower than 1×

10²¹ atoms/cm³, and

wherein at least a region of the oxide semiconductor layer includes crystals which are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

5. The semiconductor device according to claim 4, wherein a crystal structure of the crystals is represented by In₂Ga₂ZnO₇.

6. The semiconductor device according to claim 4, wherein each of the source electrode layer and the drain electrode layer comprises a conductive layer containing titanium.

7. The semiconductor device according to claim 6, wherein a resistance of the first region of the top surface of the oxide semiconductor layer which is in contact with the oxide insulating layer is higher than a resistance of a second region of the top surface of the oxide semiconductor layer which is in contact with the conductive layer.

8. The semiconductor device according to claim 4, further comprising an insulating layer over the oxide insulating layer and an electrode over the insulating layer,

wherein the electrode is electrically connected to one of the source electrode layer and the drain electrode layer.

9. The semiconductor device according to claim 4, further comprising a conductive layer overlapping with the gate electrode layer with the gate insulating layer, the oxide semiconductor layer and the oxide insulating layer interposed therebetween.

10. A semiconductor device comprising:

a gate electrode layer;

an oxide semiconductor layer comprising a first region and a second region;

a gate insulating layer between the gate electrode layer and the oxide semiconductor layer;

a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; and

an oxide insulating layer over the source electrode layer and the drain electrode layer and in contact with a first region of a top surface of the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises a channel formation region,

wherein the oxide semiconductor layer comprises In, Ga and Zn,

wherein a carbon concentration of the oxide semiconductor layer is lower than 1×

10²¹ atoms/cm³,

wherein the first region includes crystals which are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer, and

wherein the second region includes nanocrystals.

11. The semiconductor device according to claim 10, wherein a crystal structure of the crystals in the first region is represented by In₂Ga₂ZnO₇.

12. The semiconductor device according to claim 10, wherein each of the source electrode layer and the drain electrode layer comprises a conductive layer containing titanium.

13. The semiconductor device according to claim 12, wherein a resistance of the first region of the top surface of the oxide semiconductor layer which is in contact with the oxide insulating layer is higher than a resistance of a second region of the top surface of the oxide semiconductor layer which is in contact with the conductive layer.

14. The semiconductor device according to claim 10, further comprising an insulating layer over the oxide insulating layer and an electrode over the insulating layer,

wherein the electrode is electrically connected to one of the source electrode layer and the drain electrode layer.

15. The semiconductor device according to claim 10, wherein each of the nanocrystals has a particle size of greater than or equal to 1 nm and less than or equal to 20 nm.

16. The semiconductor device according to claim 10, further comprising a conductive layer overlapping with the gate electrode layer with the gate insulating layer, the oxide semiconductor layer and the oxide insulating layer interposed therebetween.