Methods of fabricating wafer-level flip chip device packages

• US 9,214,615 B2
• Filed: 10/03/2014
• Issued: 12/15/2015
• Est. Priority Date: 06/07/2012
• Status: Active Grant

• Current Assignee: Cooledge Lighting Inc.
• Original Assignee: Cooledge Lighting Inc.
• Inventors: Tischler, Michael A.
• Primary Examiner(s): Patel, Reema
• Application Number:
  US14/505,894
• Publication Number:
  US 20150076551A1
• Time in Patent Office: 438 Days
• Field of Search: 438/460, 438/464
• US Class Current: 1/1
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05638 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/0568 Molybdenum [Mo] as principal constituent
• CPC Class Codes: H01L 2224/05686 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/06102 the bonding areas being at different heights
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/27003 for holding or transferring the layer preform
• CPC Class Codes: H01L 2224/27436 : Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/29082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29298 : Fillers
• CPC Class Codes: H01L 2224/32227 : the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73104 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2933/0033 : relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0041 : relating to wavelength conversion elements
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/50 : Wavelength conversion elements
• CPC Class Codes: H01L 33/505 : characterised by the shape, e.g. plate or foil
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.

Claims

1. A composite wafer comprising:

a semiconductor substrate comprising a plurality of partially unsingulated chips, each chip comprising (i) a plurality of exposed electrical contact pads and (ii) a non-contact region disposed between the electrical contact pads;

a plurality of trenches extending through only a portion of a thickness of the substrate and partially singulating the chips; and

an anisotropic conductive adhesive (ACA) (i) on the semiconductor substrate, (ii) extending as a single unitary layer over the chips and trenches, and (iii) contacting the electrical contact pads and at least a portion of the non-contact region of each chip, a portion of the ACA directly overlying each of the trenches that partially singulate the chips,

wherein (i) none of the electrical contact pads comprises a solder bump or a non-solder bump, and (ii) no solder bumps or non-solder bumps are disposed between the electrical contact pads and the ACA.

2. The wafer of claim 1, wherein the ACA comprises an anisotropic conductive film.

3. The wafer of claim 1, wherein each chip comprises a light-emitting diode (LED) die.

4. The wafer of claim 3, wherein each LED die comprises an inorganic LED die.

5. The wafer of claim 4, wherein at least a portion of each LED die comprises a semiconductor material comprising at least one of silicon, GaAs, InAs, AlAs, InP, GaP, AlP, InSb, GaSb, AlSb, GaN, InN, AN, SiC, ZnO, or an alloy or mixture thereof.

6. The wafer of claim 1, wherein each chip comprises a laser.

7. The wafer of claim 1, wherein a thickness of the ACA across the semiconductor substrate is substantially uniform.

8. The wafer of claim 1, wherein, for each partially unsingulated chip, the top surface of each of the plurality of electrical contact pads is absolutely coplanar with or recessed below the surface of the chip surrounding the electrical contact pad.

9. The wafer of claim 1, wherein, for each partially unsingulated chip, the top surface of each of the plurality of electrical contact pads is recessed below the surface of the chip surrounding the electrical contact pad by more than 3 μ

m.

10. The wafer of claim 1, wherein, for each partially unsingulated chip, each of the plurality of electrical contact pads is in direct physical contact with (i) a semiconductor portion of the wafer thereunder and (ii) the ACA.

11. The wafer of claim 1, wherein, for each chip, the top surface of at least one of the plurality of electrical contact pads extends above the surface of the chip surrounding the electrical contact by 3 μ

m or less.

12. The wafer of claim 1, wherein, for each chip, each of the plurality of electrical contact pads comprises a metal silicide or metal nitride compound.

13. The wafer of claim 1, wherein, for each chip, each of the plurality of electrical contact pads comprises a metal layer and a second layer comprising a metal silicide or metal nitride compound.

14. The wafer of claim 1, wherein, for each chip, each of the plurality of electrical contact pads comprises at least one of Al, Cr, Ti, Au, Ni, Ag, or Mo.

15. The wafer of claim 1, wherein two of the electrical contact pads of at least one of the chips are non-coplanar.

16. The wafer of claim 1, wherein the ACA is at least partially transparent.

17. The wafer of claim 1, further comprising a protective layer disposed over at least a portion of the ACA.

18. The wafer of claim 1, wherein the ACA is activatable via application of at least one of pressure, heat, or a magnetic field.

19. The wafer of claim 17, further comprising a release film disposed over the protective layer, the release film being configured to prevent adhesion of a surface of the protective layer opposite the ACA.

20. The wafer of claim 1, further comprising a release film disposed over the ACA, the release film being configured to prevent adhesion of a surface of the ACA opposite the substrate.

21. The wafer of claim 1, wherein a surface of the ACA opposite the substrate is exposed for later adhesion.