Charge pump system
First Claim
Patent Images
1. An integrated circuit, comprising:
- a first charge pump including;
a plurality of serially arranged charge pump stages of the first charge pump arranged to pump a first voltage level from a first stage to a last stage of the first charge pump; and
inter-stage nodes between adjacent stages of the plurality of serially arranged charge pump stages; and
a second charge pump coupled to one or more of the inter-stage nodes of the first charge pump, the second charge pump arranged to pump one or more voltage levels of the one or more of the inter-stage nodes of the first charge pump, the second charge pump including;
a plurality of serially arranged charge pump stages of the second charge pump arranged to pump a second voltage level from a first stage to a last stage of the second charge pump,wherein an input clock signal received by the integrated circuit (i) determines a pumping frequency of the first charge pump, and (ii) clocks data including memory commands and memory addresses received by the integrated circuit; and
a control circuit generating a signal to enable the first charge pump in response to a read command, and providing the output of the first charge pump as a word line read voltage to a word line on the integrated circuit,wherein the first charge pump has a first pump output, the second charge pump has a second pump output, the first pump output and the second pump output are coupled in parallel to a total pump output, the first pump output coupled to the total pump output via a first transistor with a fixed diode configuration.
1 Assignment
0 Petitions
Accused Products
Abstract
In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.
38 Citations
14 Claims
-
1. An integrated circuit, comprising:
-
a first charge pump including; a plurality of serially arranged charge pump stages of the first charge pump arranged to pump a first voltage level from a first stage to a last stage of the first charge pump; and inter-stage nodes between adjacent stages of the plurality of serially arranged charge pump stages; and a second charge pump coupled to one or more of the inter-stage nodes of the first charge pump, the second charge pump arranged to pump one or more voltage levels of the one or more of the inter-stage nodes of the first charge pump, the second charge pump including; a plurality of serially arranged charge pump stages of the second charge pump arranged to pump a second voltage level from a first stage to a last stage of the second charge pump, wherein an input clock signal received by the integrated circuit (i) determines a pumping frequency of the first charge pump, and (ii) clocks data including memory commands and memory addresses received by the integrated circuit; and a control circuit generating a signal to enable the first charge pump in response to a read command, and providing the output of the first charge pump as a word line read voltage to a word line on the integrated circuit, wherein the first charge pump has a first pump output, the second charge pump has a second pump output, the first pump output and the second pump output are coupled in parallel to a total pump output, the first pump output coupled to the total pump output via a first transistor with a fixed diode configuration. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method comprising:
-
receiving, at an integrated circuit, an input clock signal that (i) determines a pumping frequency of the first charge pump, and (ii) clocks data including memory commands and memory addresses received by the integrated circuit; and pumping, on the integrated circuit, one or more voltage levels of one or more inter-stage nodes between adjacent stages of a first plurality of serially arranged charge pump stages of a first charge pump, with a second charge pump having a second plurality of serially arranged charge pump stages; enabling the first charge pump in response to a read command; and providing, from the output of the first charge pump, a word line read voltage, wherein the first charge pump has a first pump output, the second charge pump has a second pump output, the first pump output and the second pump output are coupled in parallel to a total pump output, the first pump output coupled to the total pump output via a first transistor with a fixed diode configuration. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
Specification