Triple cascode power amplifier

• US 9,214,898 B2
• Filed: 01/17/2014
• Issued: 12/15/2015
• Est. Priority Date: 01/31/2013
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Wang, Po-Chih, Ran, Gen-Sheng, Chan, Ka-Un
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US14/158,009
• Publication Number:
  US 20140210560A1
• Time in Patent Office: 697 Days
• Field of Search: 330/85, 330/116, 330/117, 330/253, 330/260, 330/275, 330/301, 330/311
• US Class Current: 1/1
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/09 A balun, i.e. balanced to or from unbalanced converter, being present at the output of an amplifier
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2203/45292 the AAC comprising biasing means controlled by the signal
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 2203/45701 the LC comprising one resistor
• CPC Class Codes: H03F 2203/45731 the LC comprising a transformer
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence

Abstract

A triple cascode power amplifier is provided. The triple cascode power amplifier includes a first-stage transistor pair, a second-stage transistor pair and a third-stage transistor pair. The first-stage transistor pair comprises two first-stage transistors that respectively receive two dynamic bias voltages with opposite polarities. The second-stage transistor pair is coupled with the first-stage transistor pair to form a first node and comprise two second-stage transistors coupled with each other to form a second node. The third-stage transistor pair is coupled with the second-stage transistor pair and comprises two third-stage transistors for outputting a differential signal. The first-stage transistor pair and the second-stage transistor pair are low voltage components while the third-stage transistor pair is a high voltage component. The power amplifier transforms the differential signal into a single-ended signal for output.

Claims

1. A triple cascode power amplifier, comprising:

a first-stage transistor pair comprising two first-stage transistors that respectively receive two dynamic bias voltages with opposite polarities;

a second-stage transistor pair coupled with the first-stage transistor pair to four a first node, the second-stage transistor pair comprising two second-stage transistors coupled with each other to form a second node; and

a third-stage transistor pair coupled with the second-stage transistor pair, the third-stage transistor pair comprising two third-stage transistors for outputting a differential signal;

wherein the first-stage transistor pair and the second-stage transistor pair are low voltage components while the third-stage transistor pair is a high voltage component; and

wherein the power amplifier transforms the differential signal into a single-ended signal for output; and

a control circuit for generating a control signal at the second node to control a voltage at the first node with respect to a ground within a predetermined range;

wherein the control circuit comprises;

an operational amplifier, a first input terminal of which receives a first voltage and an output terminal of which generates the control signal;

a first current source for supplying a current;

a second transistor, a gate of which is coupled with the output terminal of the operational amplifier to form a third node, a drain of which is coupled with the first current source and a source of which is coupled with a second input terminal of the operational amplifier to form a fourth node; and

a first transistor, a drain of which is coupled with the fourth node and a source of which is grounded;

wherein the second node is coupled to the third node;

wherein amplification coefficients of the first transistor and the first-stage transistors are proportional and amplification coefficients of the second transistor and the second-stage transistors are proportional; and

wherein a voltage at the first node varies according to a voltage at the fourth node.

2. The amplifier according to claim 1, further comprising:

a balance to unbalance unit for receiving and transforming the differential signal and generating the single-ended signal.

3. The amplifier according to claim 1, further comprising:

a dynamic bias source for generating the two dynamic bias voltages with opposite polarities.

4. The amplifier according to claim 1, wherein a voltage at the fourth node varies according to an adjustment made to the voltage at the first node.

5. The amplifier according to claim 1, wherein the control circuit further comprises:

a first resistor, a first terminal of which is coupled to the drain of the second transistor and a second terminal of which is coupled to the gate of the first transistor;

a second current source, a first terminal of which is coupled to the second terminal of the first resistor and a second terminal of which is grounded;

a second resistor, a first terminal of which is coupled to the first terminal of the second current source and a second terminal of which is coupled to one of the two dynamic bias voltages; and

a third resistor, a first terminal of which is coupled to the first terminal of the second transistor and a second terminal of which is coupled to the other dynamic bias voltage.

6. A multiple stage cascode power amplifier, comprising:

at least one first-stage transistor pair, each comprising two first-stage transistors that respectively receive two dynamic bias voltages with opposite polarities;

at least one second-stage transistor pair coupled with corresponding first-stage transistor pair to form at least one first node, each second-stage transistor pair comprising two second-stage transistors coupled with each other to form a second node; and

a third-stage transistor pair coupled with one of the at least one second-stage transistor pair, the third-stage transistor pair comprising two third-stage transistors for outputting a differential signal;

wherein the at least one first-stage transistor pair and the at least one second-stage transistor pair are low voltage components while the third-stage transistor pair is a high voltage component;

wherein each of the second-stage transistors receives a control signal at a corresponding second node to control a voltage across a corresponding first-stage transistor within a predetermined range; and

wherein the power amplifier transforms the differential signal into a single-ended signal for output; and

a control circuit for generating the control signal at the second node;

wherein the control circuit comprises;

an operational amplifier, a first input terminal of which receives a first voltage and an output terminal of which generates the control signal;

a first current source for supplying a current;

a second transistor, a gate of which is coupled with the output terminal of the operational amplifier to form a third node, a drain of which is coupled with the first current source and a source of which is coupled with a second input terminal of the operational amplifier to form a fourth node; and

a first transistor, a drain of which is coupled with the fourth node and a source of which is grounded;

wherein the second node is coupled to the third node;

wherein amplification coefficients of the first transistor and the first-stage transistors are proportional and amplification coefficients of the second transistor and the second-stage transistors are proportional; and

wherein a voltage at the first node varies according to a voltage at the fourth node.

7. A triple cascode power amplifier, comprising:

a first-stage transistor pair comprising two first-stage transistors, gates of which respectively receive a first gate voltage;

a second-stage transistor pair coupled with the first-stage transistor pair, the second-stage transistor pair comprising two second-stage transistors; and

a third-stage transistor pair coupled with the second-stage transistor pair, the third-stage transistor pair comprising two third-stage transistors for outputting a differential signal;

wherein the first-stage transistor pair and the second-stage transistor pair are low voltage components while the third-stage transistor pair is a high voltage component; and

wherein gates of the two second-stage transistors receive a control signal to control voltages across the two first-stage transistors within a predetermined range, and wherein the first gate voltages are provided according to the control signal; and

a control circuit for generating the control signal at the second node;

wherein the control circuit comprises;

an operational amplifier, a first input terminal of which receives a first voltage and an output terminal of which generates the control signal;

a first current source for supplying a current;

a second transistor, a gate of which is coupled with the output terminal of the operational amplifier to form a third node, a drain of which is coupled with the first current source and a source of which is coupled with a second input terminal of the operational amplifier to form a fourth node; and

a first transistor, a drain of which is coupled with the fourth node and a source of which is grounded;

wherein the second node is coupled to the third node;

wherein amplification coefficients of the first transistor and the first-stage transistors are proportional and amplification coefficients of the second transistor and the second-stage transistors are proportional; and

wherein a voltage at the first node varies according to a voltage at the fourth node.

8. The amplifier according to claim 7, further comprising:

a balance to unbalance unit for receiving and transforming the differential signal and generating a single-ended signal.