Memory system for error detection and correction coverage
First Claim
1. An integrated circuit buffer device, comprising:
- a first interface for communicating with a first group of memory devices; and
a second interface for communicating with a second group of memory devices,wherein the buffer device is configured to access, via the first interface, first data from the first group of memory devices and to access, via the second interface, first error information corresponding to the first data from at least one memory device in the second group of memory devices, andwherein the buffer device is configured to access, via the second interface, second data from the second group of memory devices and to access, via the first interface, second error information corresponding to the second data from at least one memory device in the first group of memory devices.
1 Assignment
0 Petitions
Accused Products
Abstract
A memory system supporting error detection and correction (EDC) coverage. The system includes a memory controller and a memory buffer. The memory buffer includes an interface to a first group of memory devices and an interface to a second group of memory devices. The memory buffer accesses data from the first group of memory devices and accesses first error information corresponding to the data from the second group of devices. The memory buffer also accesses additional data from the second group of memory devices and accesses second error information corresponding to the additional data from a device in the first group of memory devices. EDC coverage may also be configured by the memory controller so that some data accesses have EDC coverage and other data accesses do not have EDC coverage.
-
Citations
20 Claims
-
1. An integrated circuit buffer device, comprising:
-
a first interface for communicating with a first group of memory devices; and a second interface for communicating with a second group of memory devices, wherein the buffer device is configured to access, via the first interface, first data from the first group of memory devices and to access, via the second interface, first error information corresponding to the first data from at least one memory device in the second group of memory devices, and wherein the buffer device is configured to access, via the second interface, second data from the second group of memory devices and to access, via the first interface, second error information corresponding to the second data from at least one memory device in the first group of memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A memory module, comprising:
-
a first group of memory devices; a second group of memory devices; and a integrated circuit buffer device, wherein the buffer device accesses first data from the first group of memory devices and accesses first error information corresponding to the first data from at least one memory device in the second group of memory devices, and wherein the buffer device accesses second data from the second group of memory devices and accesses second error information corresponding to the second data from at least one memory device in the first group of memory devices.
-
-
12. A method of operation of an integrated circuit buffer device, the method comprising:
-
accessing first data from a first group of memory devices and accessing first error information corresponding to the first data from at least one memory device in a second group of memory devices; and accessing second data from the second group of memory devices and accessing second error information corresponding to the second data from at least one memory device in the first group of memory devices. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
-
Specification