Microelectronic packages and methods therefor

• US 9,218,988 B2
• Filed: 04/01/2014
• Issued: 12/22/2015
• Est. Priority Date: 12/23/2005
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Kang, Teck-Gyu, Mohammed, Ilyas, Chau, Ellis
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US14/242,279
• Publication Number:
  US 20140213021A1
• Time in Patent Office: 630 Days
• Field of Search: 257/678, 257/686, 257/E21.499, 438/109, 438/110, 438/112, 438/127
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials.

Claims

1. A method of making a microelectronic assembly comprising:

providing a microelectronic package including a substrate, a microelectronic element overlying said substrate and at least two conductive elements projecting from a surface of said substrate, first and second conductive elements of said at least two conductive elements having surfaces remote from said surface of said substrate and being electrically connected through said substrate to said microelectronic element for carrying a first signal electric potential on said first conductive element and for simultaneously carrying a second electric potential on said second conductive element, said second electric potential being different from said first signal electric potential;

molding a dielectric material around said at least two conductive elements for supporting said microelectronic package, the molding performed by introducing the dielectric material into an interior cavity of a mold in which said conductive elements are disposed, the mold having depressions provided in a interior surface thereof, the depressions aligned with the at least two conductive elements so that the at least two conductive elements extend into the depressions when the dielectric material is introduced therein, and so that as a result of said molding said remote surfaces of said at least two conductive elements remain accessible and exposed at an exterior surface of said molded dielectric material and said remote surfaces are at least substantially planar and project to heights from said surface of said substrate greater than a height of the exterior surface of the molded dielectric material from said surface of said substrate.

2. The method as claimed in claim 1, wherein said molded dielectric material surrounds at least portions of individual ones of said at least two conductive elements.

3. The method as claimed in claim 1, wherein said at least two conductive elements project from a first surface of said substrate and said substrate further comprises a second surface remote from said first surface and at least a third conductive element and a fourth conductive element projecting from said second surface of said substrate, said at least third and fourth conductive elements having surfaces remote from said second surface of said substrate and being electrically connected through said substrate to said microelectronic element for carrying a third signal electric potential on said third conductive element and for simultaneously carrying a fourth electric potential on said fourth conductive element, said fourth electric potential being different from said third signal electric potential.

4. The method as claimed in claim 3, further comprising compressing said at least third and fourth conductive elements so that said remote surfaces of said at least two second conductive elements lie in a common plane.

5. The method as claimed in claim 3, wherein said substrate is flexible.

6. The method as claimed in claim 3, wherein said substrate comprises a polymeric material.

7. The method as claimed in claim 3, wherein said microelectronic element is a semiconductor chip having a front face and contacts at said front face, and a back face remote therefrom, said front face facing said substrate.

8. The method as claimed in claim 3, wherein said microelectronic element is a semiconductor chip having a front face and contacts at said front face, and a back face remote therefrom, said back face facing said substrate.

9. The method as claimed in claim 3, further comprising a compliant layer disposed between said microelectronic element and said substrate.

10. The method as claimed in claim 3, wherein at least some of said conductive elements and said microelectronic element overlie a first surface of said substrate.

11. The method as claimed in claim 3, wherein said microelectronic element overlies a first surface of said substrate and at least some of said conductive elements overlie a second surface of said substrate remote opposite said first surface.

12. The method as claimed in claim 3, wherein said substrate includes a plurality of dielectric layers and conductive traces extending along said dielectric layers.

13. The method as claimed in claim 3, wherein said microelectronic package is a first microelectronic package, further comprising making a second microelectronic package using the method of claim 3, and stacking said second microelectronic package atop said first microelectronic package, wherein said first and second microelectronic packages are electrically interconnected together through said at least two conductive elements of each of said first and second microelectronic packages.

14. A method of making a microelectronic assembly comprising:

providing a structure including a substrate having first and second oppositely facing surfaces, a microelectronic element overlying the first surface of said substrate, a plurality of first conductive elements extending above the first surface and having remote surfaces above the first surface, said first conductive elements being electrically connected with said microelectronic element through electrically conductive traces on said substrate, said structure further including a plurality of second conductive elements accessible at the second surface of said substrate for connection with a component external to said structure, said second conductive elements electrically interconnected with said first conductive elements and with said microelectronic element;

molding a dielectric material covering portions of said first conductive elements and overlying at least a portion of said first surface, the molding performed by introducing the dielectric material into an interior cavity of a mold in which said first conductive elements are disposed, wherein during the introducing of the dielectric material said remote surfaces of said first conductive elements are protected from contact with the dielectric material, such that as a result of said molding said remote surfaces of said first conductive elements project above an exterior surface of said molded dielectric material.

15. The method of claim 14, wherein the molding is performed such that said remote surfaces are planarized.

16. The method as claimed in claim 15, wherein said molding comprises compressing at least some of said first conductive elements so that remote surfaces of said at least some first conductive elements lie in a common plane.

17. The method as claimed in claim 14, wherein said substrate includes at least one dielectric layer and conductive traces extending along and supported by said at least one dielectric layer, wherein said molded dielectric material extends from a surface of a dielectric layer of said at least one dielectric layer.